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Microwave, MTT-S International Symposium

作者： S. Stefanou J.S. Hamel M. Bain P. Baine B.M. Armstrong H.S. Gamble R. Mauntel M. Haung Department of Electronics and Computer Science University of Southampton Southampton UK Department of Electrical and Computer Engineering University of Waterloo Waterloo ON Canada School of Electrical and Electronic Engineering Queen's University of Belfast Belfast UK School of Electrical and Electronic Engineering Queen''s University Belfast Belfast UK Semiconductor Products Sector Motorola Inc. Pheonix Arizona

The physical mechanisms responsible for superior crosstalk suppression are identified in a new class of silicon-on-insulator substrate (GPSOI) that incorporates a buried metallic ground plane below the active silicon and buried oxide layers. It has been shown that this technology exhibits a factor of ten reduction in crosstalk power between components through the substrate compared to existing state-of-the-art silicon-based substrates using standard s/sub 21/ magnitude measurements in a microwave coplanar transmission test structure. The dominant crosstalk mechanisms are identified and compared to other existing crosstalk suppression technologies using numerical electromagnetic simulations and lumped element compact model development.

关键词： Physics Crosstalk Silicon on insulator technology Microwave technology Measurement standards Power measurement Microwave measurements Electromagnetic measurements Testing Numerical simulation

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A quantitative approach to nonlinear process design rule scaling [VLSI]

A quantitative approach to nonlinear process design rule sca...

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1999 Conference on Advanced Research in VLSI, ARVLSI 1999

作者： Gold, Spencer M. Bernhardt, Bruce Brown, Richard B. Electrical Engineering and Computer Science Dept. University of Michigan Ann ArborMI United States Networking and Computing Systems Group Semiconductor Product Sector Motorola Inc. TempeAZ United States

ISBN: (纸本)0769500560

This paper describes a quantitative methodology for selecting nonlinear design rule scale factors that provide the most cost-efficient improvements in IC performance and area. The methodology includes identifying the design rules which have the greatest impact on the scaling objective and analyzing the area and performance improvements as these rules are scaled through a range of practical scale factors. Power and delay improvement data are then combined with die cost estimates to produce a cost/benefit ratio, a quantitative metric for design rule scaling cost-efficiency. The slopes and inflection points of cost/benefit vs. scale factor plots will guide process engineers in selecting scale factors for the various design rules. This procedure is repeated using the results of one iteration as the starting point for the next. The cost/benefit analysis methodology is demonstrated by comparing embedded static RAMs implemented in a complementary GaAs (CGaAsTM) process. The SRAMs are generated by a process-independent, optimizing SRAM compiler which can create SRAM macrocells for any complementary technology. A cost/benefit analysis of the CGaAs design rules shows that when operating under a fixed spending cap for process scaling research, development, and capital equipment acquisition, nonlinear scaling can provide greater improvements in area and performance than linear scaling. The results also show that for a 0.5 μm CGaAs process to be fabricated in high volume, the first scaling step should be a 30% reduction of the source drain area and via/metal pitch, gate metal to ohmic spacing, and gate metal spacing design rules. © 1999 IEEE.

关键词： Cost benefit analysis

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An efficient method for hot-spot identification in ULSI circuits 99

An efficient method for hot-spot identification in ULSI circ...

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IEEE International Conference on computer-Aided Design

作者： Yi-Kan Cheng Sung-Mo Kang Semiconductor Products Sector Somerset Design Center Motorola Inc. Austin TX USA Coordinated Science Laboratory Department of Electrical and Computer Engineering University of Illinois Urbana IL USA

ISBN: (纸本)0780358325

In this paper, we present a method to efficiently identify the on-chip hot spots in ULSI circuits. A set of mathematical formulae were derived in analytical forms so that local temperature information can be fetched quickly. These formulae were based on the Green's function and error function approximation, and the resulting equations were further simplified to a tractable level by asserting different constraints. Experimental result shows that this method is able to accurately locate the hot spots with little time complexity. It is particularly useful for temperature-driven circuit macro placement in the early chip design phase, for which a large number of design iterations are needed and simulation efficiency is required.

关键词： Ultra large scale integration Circuits Temperature Electrothermal effects Computational modeling Very large scale integration Thermal conductivity Heat transfer US Department of Transportation Information analysis

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A quantitative approach to nonlinear process design rule scaling [VLSI]

A quantitative approach to nonlinear process design rule sca...

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Conference on Advanced Research in VLSI

作者： S.M. Gold B. Bernhardt R.B. Brown Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA Networking and Computing Systems Group Semiconductor Products Sector Motorola Inc. Tempe AZ USA

This paper describes a quantitative methodology for selecting nonlinear design rule scale factors that provide the most cost-efficient improvements in IC performance and area. The methodology includes identifying the design rules which have the greatest impact on the scaling objective and analyzing the area and performance improvements as these rules are scaled through a range of practical scale factors. Power and delay improvement data are then combined with die cost estimates to produce a cost/benefit ratio, a quantitative metric for design rule scaling cost-efficiency. The slopes and inflection points of cost/benefit vs. scale factor plots will guide process engineers in selecting scale factors for the various design rules. This procedure is repeated using the results of one iteration as the starting point for the next. The cost/benefit analysis methodology is demonstrated by comparing embedded static RAMs implemented in a complementary GaAs (CGaAs/sup TM/) process. The SRAMs are generated by a process-independent, optimizing SRAM compiler which can create SRAM macrocells for any complementary technology. A cost/benefit analysis of the CGaAs design rules shows that when operating under a fixed spending cap for process scaling research, development, and capital equipment acquisition, nonlinear scaling can provide greater improvements in area and performance than linear scaling. The results also show that for a 0.5 /spl mu/m CGaAs process to be fabricated in high volume, the first scaling step should be a 30% reduction of the source drain area and via/metal pitch, gate metal to ohmic spacing, and gate metal spacing design rules.

关键词： Process design Performance analysis Delay estimation Cost benefit analysis Random access memory Design engineering Power engineering and energy Gallium arsenide Optimizing compilers Macrocell networks

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Temperature-driven power and timing analysis for CMOS ULSI circuits

Temperature-driven power and timing analysis for CMOS ULSI c...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Yi-Kan Cheng Sung-Mo Kang Somerset Design Center Semiconductor Products Sector Motorola Inc. Austin TX USA Coordinated Science Laboratory Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign Urbana IL USA

In this paper, we present a temperature-driven simulation framework for power and timing analysis of CMOS ULSI circuits. A Monte-Carlo based power and temperature iteration methodology is first employed for finding the nominal steady-state on-chip temperature profile. The temperature information and the input vectors used in power analysis are then utilized for temperature-dependent timing analysis. Simulation results show that the on-chip temperature gradient and temperature rise has great impact on circuit timing, and our tool provides important guidelines for thermally reliable ULSI circuit design and to enhance the overall chip performance.

关键词： Timing Ultra large scale integration Temperature distribution Circuit simulation Packaging Steady-state Frequency estimation Temperature measurement Equations Product design

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Ethics and the privacy of electronic mail

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Information Society 1995年第3期11卷 223-235页

作者： Doss, Erini Loui, Michael C. Department of Electrical and Computer Engineering and Coordinated Science Laboratory and University of Illinois at Urbana‐Champaign Urbana IL United States Motorola Land Mobile Products Sector Schaumburg IL 60196 1301 E. Algonquin Rd United States

After reviewing legal and philosophical definitions of privacy, and their justifications, we consider whether electronic mail (e‐mail) should be private. Currently, most universities treat e‐mail as private, and most corporations do not. Federal and state laws protect the privacy of e‐mail only in public networks. We conclude by arguing why e‐mail should be private everywhere, for ethical reasons. © 1995 Crane, Russak & Company, Inc.

关键词： E-mail Electronic mail Ethics Privacy

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Improving software quality through a novel testing strategy

Improving software quality through a novel testing strategy

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IEEE Annual International computer Software and Applications Conference (COMPSAC)

作者： Xiaomu Zeng J.J.P. Tsai T.J. Weigert Department of Electrical Engineering and Computer Science University of Illinois Chicago Chicago IL USA Land Mobile Products Sector Motorola Inc. Schaumburg IL USA

A general approach to test case generation relying on a novel testing method is presented. We also evaluate theoretically how generated test cases will contribute to, for example, the verification criterion, when attempting to establish the correctness of a program. Our testing methods have much smaller complexity when applied to well structured programs of at least moderate size, and have better conformance, as compared to existing data flow coverage and control flow coverage oriented testing methods.

关键词： Software quality Software testing Logic testing Polynomials computer science Mobile computing Size control Formal specifications Automatic testing Fault detection

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Accurate yield estimation of circuits with redundancy

Accurate yield estimation of circuits with redundancy

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： D.D. Gaitonde D.M.H. Walker W. Maly Advanced Design Technology Semiconductor Products Sector Motorola Inc. Tempe AZ USA Department of Computer Science Texas A and M University TX USA Department of Electrical & Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Yield concerns owing to increasing die sizes have prompted designers to include redundant elements in the design. In this paper we present a technique for accurately estimating the yield of designs that employ redundancy. We show that conventional techniques that do not take into account the actual chip layout and defect statistics could result in substantial error in the yield estimate. We show that the optimum amount and nature of redundancy depends heavily on the nature of the the circuit, the chip layout and defect statistics.

关键词： Yield estimation Redundancy Manufacturing Circuit faults Fault diagnosis Clocks computer science Design engineering Error analysis Statistics

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Zero-voltage-transition converters using an inductor feedback technique

Zero-voltage-transition converters using an inductor feedbac...

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Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： J.P. Gegner C.Q. Lee Land Mobile Products Sector Motorola Inc. Schaumburg IL USA Power Electronics Research Laboratory Department of Electrical Engineering and Computer Science (MIC 154) University of Illinois Chicago Chicago IL USA

A technique using inductor feedback is presented for achieving zero-voltage switching (ZVS) in PWM controlled topologies. These converters exhibit low voltage and current stresses characteristic of hard-switched PWM converters, yet achieve ZVS with minimal current and voltage rating of the auxiliary soft-switching circuitry. Based on this technique, an experimental 730 W, 300 kHz boost converter is designed for universal off-line power factor correction. A complete analysis and a design procedure are also presented.< >

关键词： Inductors Feedback Switches Zero voltage switching Switching circuits Stress Resonance Circuit topology Low voltage Rectifiers

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Zero-voltage-switching converters with multi-resonant bipolar switch

Zero-voltage-switching converters with multi-resonant bipola...

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Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： J.P. Gegner C.Q. Lee Land Mobile Products Sector Motorola Inc. Schaumburg IL USA Department of Electrical Engineering and Computer Science (M/C 154) University of Illinois Chicago Chicago IL USA

Full-wave mode operation of zero-voltage-switched (ZVS) power converters may be losslessly implemented by splitting the resonant capacitor across both the active switch (MOSFET) and the series diode. By appropriately choosing the relative size of each capacitor, charge otherwise trapped inside the MOSFET output capacitance at turn-on may be recirculated through the second capacitor, realizing true zero-voltage-switching. Improved load regulation of ZVS converters (such as ZVS-QRCs) is thereby achieved without sacrificing efficiency at high frequencies. Analysis, simulation, and experimental verification are presented.< >

关键词： Capacitors Zero voltage switching Switches MOSFET circuits Switching converters Resonance Power MOSFET Diodes Capacitance Frequency conversion

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