A memory cell design and fabrication process for high performance SRAMs are described. Stacked Split Word-Line cell architecture achieves 7.16/spl mu/m/sup 2/ cell area with relaxed 0.4/spl mu/m design rule. Pull-down...
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A memory cell design and fabrication process for high performance SRAMs are described. Stacked Split Word-Line cell architecture achieves 7.16/spl mu/m/sup 2/ cell area with relaxed 0.4/spl mu/m design rule. Pull-down and access transistors of the memory cell are carefully and independently designed to enhance cell stability. High performance polysilicon thin film transistor is realized by channel polysilicon oxidation and oxygen assisted hydrogen passivation into channel polysilicon. Fabrication process steps are designed to reduce mechanical stress that causes large memory cell leakage and degrades data retention stability.
Negative bias-temperature (NBT) instability of polysilicon thin film transistors (TFTs) has been studied. We found water is strongly related to this phenomenon and can result in a threshold voltage shift of 1 V or mor...
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Negative bias-temperature (NBT) instability of polysilicon thin film transistors (TFTs) has been studied. We found water is strongly related to this phenomenon and can result in a threshold voltage shift of 1 V or more within a short time under NBT stress. This paper shows the results supporting this fact and proves, by using thin LPCVD SiN films, the suppression of water penetration and/or content in the oxides is essential in reducing this instability to an acceptable level. A qualitative model is presented to explain the role of water and experimental results.< >
Stacked Split Word-Line cell technology suitable for low voltage operation, large capacity and high speed SRAMs has been proposed. Two pull-down transistors and two access transistors are fabricated employing two sepa...
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Stacked Split Word-Line cell technology suitable for low voltage operation, large capacity and high speed SRAMs has been proposed. Two pull-down transistors and two access transistors are fabricated employing two separate gate formations. A pair of split word-lines is stacked over pull-down transistors. That permits large cell ratio in small cell area and independent optimization of pull-down and access transistors. Threshold voltage of access transistors is lowered to improve cell stability. Top gate thin film polysilicon transistor and Vcc plate are used to make cell node capacitor and improve soft error immunity. This technology is applied to a fast 16M bit SRAM and enabled a 7.16 /spl mu/m/sup 2/ cell area in relaxed 0.4 /spl mu/m layout rule utilizing conventional i-line stepper without phase-shift masks.< >
The relationship between ESD performance and photon emission from MOSFETs under breakdown conditions has been studied for various drain structures. Since ESD protection level is well correlated with current driveabili...
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The relationship between ESD performance and photon emission from MOSFETs under breakdown conditions has been studied for various drain structures. Since ESD protection level is well correlated with current driveability in the second breakdown region, observation of the spatial distribution of photon emission provides new insight to the understanding of breakdown behaviors resulting in different ESD performance. The photon emission study revealed that the three-dimensional progression of breakdown behaviors depends on drain structures and are correlated with ESD performance.< >
Fabrication process is designed to minimize mechanical stress in semiconductor devices and to improve device reliability. Mechanical stress levels were predicted by simulation then TEM analysis was performed to evalua...
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Fabrication process is designed to minimize mechanical stress in semiconductor devices and to improve device reliability. Mechanical stress levels were predicted by simulation then TEM analysis was performed to evaluate critical stress that generates dislocations. This gives us design guidelines for small geometry LOCOS process. Polysilicon thickness in the W polycide gate electrode is designed to minimize mechanical stress in the gate oxide and to suppress gate oxide failure in probe and class tests. Moreover, critical stress to generate dislocations during post source/drain ion implantation anneal is obtained by a ball indentation method. This indicated that lower temperature anneal is effective to suppress dislocations. Two-step anneal is introduced to suppress dislocations to enable higher ion activation.
The structure and orientation of cobalt films several hundred Å thick formed on cleavage faces of rocksalt and mica by vacuum evaporation under the pressure of 10-7-10-6 Torr have been studied by transmission ele...
An ozone etching process for Ru was studied. Ru was etched at an extremely high rate of 950 nm/min at temperatures between 100°C and 150°C. The main etching product was RuO4, and the etch rate was proportion...
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An ozone etching process for Ru was studied. Ru was etched at an extremely high rate of 950 nm/min at temperatures between 100°C and 150°C. The main etching product was RuO4, and the etch rate was proportional to the first order of the ozone concentration. At temperatures above 150°C, RuO2 hindered the etching reaction. A comparison between the etching reaction of Ru and that of photoresist revealed that Ru was etched mainly by ozone, whereas photoresist was etched mainly by atomic oxygen. The difference in reactions enabled to control the etch selectivity between Ru and photoresist purely by manipulating the reaction temperature.
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