检索结果-内蒙古大学图书馆

Multi-mode Data Processing Electronics for VELC payload of Aditya-L1

Journal of Spacecraft Technology 2024年第1期35卷 45-52页

作者： Singh, Namita Desai, Jalshri Kumaran, Rajiv Paul, Sandip Gupta, Vivek Ahmedabad India Electro-optical System Design and Integration Group Sensor Development Area SAC Ahmedabad India

In current scenarios, major space based scientific applications demand high-speed, ultra-low noise electronics systems with onboard intelligence catering to various operational modes for achieving demanding science goals. For space applications, it further becomes necessary to ease down the demand on total data volume without compromising the science goals. This calls for intensive on-board processing and a high level of ground programmability through tele-command. This paper discusses design configuration, methodology and significant challenges in the development of on-board Digital Processing and Control Electronics (DPCE) targeting solar observation and studies with a wide FOV (Field of View), high electronics SNR requirement and multiple on-board algorithms for operating modes and optimization of data volume. © 2024, ISRO Satellite Centre. All rights reserved.

关键词： Space applications

来源：评论

学校读者我要写书评

暂无评论

High Performance Detector Electronics for VELC payload of Aditya-L1

引用

Journal of Spacecraft Technology 2024年第1期35卷 53-63页

作者： Kumar, Ashok Kumaran, Rajiv Desai, Jalshri Singh, Namita Kumar, Ravi Srivastava, Anuj Nandha, P. Gupta, Vivek Shah, Dhrupesh Kumar, Jitendra Gupta, Sanjay Kumar Pandey, Deep Ahmedabad India Electro-optical System Design and Integration Group Sensor Development Area SAC Ahmedabad India Optical Payload Mechanical Group Mechanical Engineering System Area SAC Ahmedabad India Electronics Fabrication & Maintenance Group Electronics Support & Test Service Area SAC Ahmedabad India

Aditya-L1, ISRO’s first solar observatory is carrying out the study of sun from L1-Lagrange point with its suite of seven instruments. Visible Emission Line Coronagraph (VELC) is one such instrument, which will provide observations close to solar limb with internal occultation in visible and near infrared (IR) region. This paper provides details of design and development of electronics for continuum, two spectroscopic and spectro- polarimetry channels of VELC instrument. These are realized using sCMOS detectors in visible and two spectroscopic chains respectively. Developed hardware comprises of detector front-end electronics, control and data processing electronics and DC-DC converter electronics. On-board intelligence algorithm is implemented for detection of Coronal Mass Ejection (CME) events. Payload is designed to have ultra-high sensitivity (noise equivalent signal = 0.2 photon/sec/pixel). Dark noise of 120 dB with single photon detection capability and 18-bit radiometric resolution. Imaging with simulated target (with input of 15-photon max.) was carried out. These VELC performances are best among worldwide solar coronagraphs satellite. Control of instrument background is critical to achieve the desired scientific goal. Hence stringent contamination control protocols were evolved and implemented during all stages of payload development. The instrument (all 4-channels) consumes 105W of power, is realized with mass © 2024, ISRO Satellite Centre. All rights reserved.

关键词： Instrument testing

来源：评论

学校读者我要写书评

暂无评论

RF models for Through SiC Vias for Highly Integrated Interposer Technology

RF models for Through SiC Vias for Highly Integrated Interpo...

引用

2023 Smart systems integration Conference and Exhibition, SSI 2023

作者： Koszegi, Julia-Marie MacKowiak, Piotr Stocker, Robert Ndip, Ivan Schiffer, Michael Schneider-Ramelow, Martin Rf and Smart Sensor Systems Fraunhofer Izm Berlin Germany Wafer Level System Integration Fraunhofer Izm Berlin Germany Technische Universität Berlin Fraunhofer Izm Berlin Germany

ISBN: (纸本)9798350325065

This paper we will analyzes the parameter space given by present manufacturing technology of TSiCVs and compares it to standard TSV values. Beside the different geometries available in TSiCV technology, the resistivity of the material is known to be a key parameter as studies on low, medium and high resistivity silicon have indicated previously. A full wave simulation model is presented and the applicability of analytical models known from TSVs adapted for TSiCVs is discussed. The RF modeling of TSiCVs is the next crucial step to optimize manufacturing of TSiCVs for RF needs and to fully integrate a broad spectrum of functionalities on one SiC platform. © 2023 IEEE.

关键词： Silicon carbide

来源：评论

学校读者我要写书评

暂无评论

TSiCV Based Silicon Carbide Interposer Technology

TSiCV Based Silicon Carbide Interposer Technology

引用

2023 Smart systems integration Conference and Exhibition, SSI 2023

作者： MacKowiak, Piotr Koszegi, Julia-Marie Schneider-Ramelow, Martin Schiffer, Michael Fraunhofer Izm Dept. Wafer Level System Integration Berlin Germany Fraunhofer Izm Dept. Rf & Smart Sensor System Berlin Germany Technische Universität Berlin Dept. Technologien der Mikroperipherik Berlin Germany

ISBN: (纸本)9798350325065

This paper describes the research on the development on SiC Interposer technology with Through SiC Vias (TSiCV). It demonstrates a SiC Interposer with the Flip-Chip assembled Chips with different thicknesses. It gives an overview over the different approaches of via formation and describes the fabrication of a SiC Interposer. It highlights the differences between the via formation between silicon and silicon carbide. The etching of SiC itself is described and two different isolation methods for the vias are discussed. Furthermore, two different methods to access the backside of the via are presented. The via diameters between 40 μm to 120 μm have been investigated and etch rates of up to 2 μm/min were achieved. A discussion about the possibilities and limitation of the different approaches are presented. © 2023 IEEE.

关键词： Silicon carbide

来源：评论

学校读者我要写书评

暂无评论

integration of III-V Components of 5G Transceiver in Embedding PCB-Based Technology

Integration of III-V Components of 5G Transceiver in Embeddi...

引用

Electronics system-integration Technology Conference, ESTC

作者： Tekfouy Lim Stefan Kosmider Kavin Senthil Murugesan Andreas Ostmann Fraunhofer IZM RF & Smart Sensor Systems Berlin Germany Fraunhofer IZM System Integration & Interconnection Technologies Berlin Germany Technical University Berlin Berlin Germany

ISBN: (数字)9798350390360

ISBN: (纸本)9798350390377

III-V technology provides improved the RF performances in term of output power compared with standard CMOS technology. However, their integration into a system is challenging due to their thin top level contact made out of gold. Because of that, standard bumping cannot be applied. This paper presents the embedding PCB-based technology from Fraunhofer IZM which can embed the III-V active components (in this case from GaN technology) in different 5G/6G mm-wave frequency bands (39 GHz and 170 GHz). This technology enables the integration of antennas within the module, utilizing the Antenna in Package (AiP) topology. This integration reduces the overall size of the system, providing a compact solution.

关键词： Radio frequency Gold 5G mobile communication CMOS technology Transceivers Topology Standards Antennas Power generation

来源：评论

学校读者我要写书评

暂无评论

RF models for Through SiC Vias for Highly Integrated Interposer Technology

RF models for Through SiC Vias for Highly Integrated Interpo...

引用

Smart systems integration (SSI)

作者： Julia-Marie Köszegi Piotr Mackowiak Robert Stöcker Ivan Ndip Michael Schiffer Martin Schneider-Ramelow RF and Smart Sensor Systems Fraunhofer IZM Berlin Germany Wafer Level System Integration Fraunhofer IZM Berlin Germany Fraunhofer IZM Technische Universität Berlin Berlin Germany

关键词：

来源：评论

学校读者我要写书评

暂无评论

TSiCV Based Silicon Carbide Interposer Technology

TSiCV Based Silicon Carbide Interposer Technology

引用

Smart systems integration (SSI)

作者： Piotr Mackowiak Julia-Marie Köszegi Martin Schneider-Ramelow Michael Schiffer Dept. Wafer Level System Integration Fraunhofer IZM Berlin Germany Dept. RF & Smart Sensor System Fraunhofer IZM Berlin Germany Dept. Technologien der Mikroperipherik Technische Universität Berlin Berlin Germany

关键词：

来源：评论

学校读者我要写书评

暂无评论

Versatile Hermetically Sealed sensor Platform for High Frequency Applications 23

Versatile Hermetically Sealed Sensor Platform for High Frequ...

引用

23rd European Microelectronics and Packaging Conference and Exhibition, EMPC 2021

作者： Kröhnert, Kevin Wöhrmann, Markus Schiffer, Michael Friedrich, Georg Starukhin, Dzmitry Schneider-Ramelow, Martin Mayer, Winfried Chaloun, Tobias Galler, Thomas Waldschmidt, Christian Schulz-Ruhtenberg, Malte Ambrosius, Norbert Hansen, Ulli Wafer Level System Integration Fraunhofer IZM Berlin Germany R&D Pactech GmbH Nauen Germany Sensor Development Sentronics Metrology GmbH Mannheim Germany Technical University Berlin Berlin Germany Endress+Hauser Maulburg Germany Universität Ulm Ulm Germany LPKF Laser & Electronics AG Garbsen Germany MSG Lithoglas GmbH Berlin Germany

ISBN: (纸本)9780956808677

In this work, we present the realized versatile hermetically sealed sensor packaging platform based on glass interposers which is applicable in industrial metrology, MEMS, photonics, life sciences and process automation application, among others. The sealed glass package can include passives and different active devices (radar, pressure, infrared sensors, etc.). Glass is used because it offers ideal properties for such a package by providing excellent chemical resistance, mechanical strength, advantageous RF characteristics and low costs. The capabilities of the platform are demonstrated in form of a radar level sensor which is operated at 160GHz. The level sensor includes our sensor packaging platform with an integrated SiGe ASIC and an RF port. Due to the hermetic sealing of the ASIC inside, it is possible to utilize the package in hazardous environments, in this case in chemical microreactors. The package only measures 5.9 x 4.4 x 0.8 mm3 and uses TGVs (Through-Glass Vias) in this miniaturized sensor systems as vertical DC and RF interconnections with low parasitics which leads to low losses, while maintaining hermetic sealing. The performance of the TGVs regarding their reliability and their RF capabilities was investigated before and showed superior properties with less effort for fabrication. In this paper we will focus on all aspects of the final package with a fully functional radar ASIC inside. We consider the processing chain based on wafer-level processes, design and simulation, the analysis of the realized radar sensor demonstrator as well as the characterization and evaluation of the final package regarding reliability and hermeticity. The glass interposer processing steps and all the challenges which had to be solved for the via formation, the TGV filling and the hermetically sealing of the two interposers with the ASIC inside will be highlighted. The characterization and evaluation of the novel demonstrator system will consider RF performance, radar c

关键词： Glass

来源：评论

学校读者我要写书评

暂无评论

Reliabillity of Through Glass Vias and hermetically sealing for a versatile sensor plattform

Reliabillity of Through Glass Vias and hermetically sealing ...

引用

Electronics system-integration Technology Conference, ESTC

作者： Kevin Kröhnert Georg Friedrich Dzmitry Starukhin Markus Wöhrmann Michael Schiffer Martin Schneider-Ramelow Wafer Level System Integration Fraunhofer IZM Berlin Germany R&D Pactech GmbH Nauen Germany Sensor Development Sentronics metrology GmbH Mannheim Germany Technical University Berlin Berlin Germany

ISBN: (数字)9781728162935

ISBN: (纸本)9781728162942

In this work we present aspects of our versatile hermetically sealed sensor platform. The sealed glass package can include passive and active devices (radar, pressure, infrared sensors). Glass is used due to its ideal properties for such applications, like excellent chemical resistance, mechanical strength and low costs. The hermetic sealing allows seamless operation in hazardous environments. The tgvs (Through - Glass - Vias) may be deployed, for instance, in miniaturized sensor systems as vertical DC and RF interconnections with reduced parasitics for improved performance of the sealed device, while maintaining hermetic sealing. Tgvs improve the performance drastically and will provide a hermitically sealed connection to the inner circuitries of the package. This approach was previously compared regarding their RF properties to the conventional approach and showed superior properties with less effort for fabrication [1] [2] [3]. In this paper we focus on three aspects of the package, the wafer-to-wafer bonding techniques for the sealing of the package, the reliability of the tgv integration in the interposer, and the heat dissipation through the tgvs. For the sealing, SAC 305 solder balls are used. Using the Pactech SB 2 -Jet high-speed sequential solder-ball attach and laser reflow process, we are able to create a continuous layer of solder around a seal ring and place a solder ball on top of each I/O (Input/Output) pad. The pads are used to transmit signals from the bottom of the interposer to the top wafer, which will then contact the ASIC pads. The system is capable to singulate, to position and to reflow solder balls with a diameter between 40 μm and 760 μm. A big variety of different solder material e.g. SnAgAu, SnAu, InSn, SnBi is applicable. Due to the use of a laser reflow process no flux is needed. For wafer bonding, a wafer-to-wafer bonder is utilized to heat the wafers and bring them into contact. To create a defined separation between both bonding par

关键词： Glass Copper Resistance Semiconductor device reliability Reliability Strips Electrical resistance measurement

来源：评论

学校读者我要写书评

暂无评论

Versatile Hermetically Sealed sensor Platform for High Frequency Applications

Versatile Hermetically Sealed Sensor Platform for High Frequ...

引用

European Microelectronics and Packaging Conference, EMPC

作者： Kevin Kröhnert Markus Wöhrmann Michael Schiffer Georg Friedrich Dzmitry Starukhin Martin Schneider-Ramelow Winfried Mayer Tobias Chaloun Thomas Galler Christian Waldschmidt Malte Schulz-Ruhtenberg Norbert Ambrosius Ulli Hansen Wafer Level System Integration Fraunhofer IZM Berlin Germany R&D Pactech GmbH Nauen Germany Sensor Development Sentronics metrology GmbH Mannheim Germany Technical University Berlin Berlin Germany Endress + Hauser Maulburg Germany Universität Ulm Ulm Germany LPKF Laser & Electronics AG Garbsen Germany MSG Lithoglas GmbH Berlin Germany

In this work, we present the realized versatile hermetically sealed sensor packaging platform based on glass interposers which is applicable in industrial metrology, MEMS, photonics, life sciences and process automation application, among others. The sealed glass package can include passives and different active devices (radar, pressure, infrared sensors, etc.). Glass is used because it offers ideal properties for such a package by providing excellent chemical resistance, mechanical strength, advantageous RF characteristics and low costs. The capabilities of the platform are demonstrated in form of a radar level sensor which is operated at 160GHz. The level sensor includes our sensor packaging platform with an integrated SiGe ASIC and an RF port. Due to the hermetic sealing of the ASIC inside, it is possible to utilize the package in hazardous environments, in this case in chemical microreactors. The package only measures 5.9 x 4.4 x 0.8 mm 3 and uses TGVs (Through-Glass Vias) in this miniaturized sensor systems as vertical DC and RF interconnections with low parasitics which leads to low losses, while maintaining hermetic sealing. The performance of the TGVs regarding their reliability and their RF capabilities was investigated before and showed superior properties with less effort for fabrication. In this paper we will focus on all aspects of the final package with a fully functional radar ASIC inside. We consider the processing chain based on wafer-level processes, design and simulation, the analysis of the realized radar sensor demonstrator as well as the characterization and evaluation of the final package regarding reliability and hermeticity. The glass interposer processing steps and all the challenges which had to be solved for the via formation, the TGV filling and the hermetically sealing of the two interposers with the ASIC inside will be highlighted. The characterization and evaluation of the novel demonstrator system will consider RF performance, radar

关键词： Fabrication Semiconductor device reliability Radar Glass Packaging Loss measurement sensor systems

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：