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IIAI International Conference on Advanced Applied Informatics (IIAIAAI)

作者： Jun Zeng Feng Li Haiyang Liu Junhao Wen Sachio Hirokawa Key Laboratory of Dependable Service Computing in Cyber Physical Society Chongqing University Chongqing China Graduate School of Software Engineering Chongqing University Chongqing China School of Software Engineering Chongqing University Chongqing China Research Institute for Information Technology Kyushu University Fukuoka Japan

ISBN: (纸本)9781467389860

Recommender system is an effective way to help users to obtain the personalized and useful information. However, due to complexity and dynamic, the traditional recommender system cannot work well in mobile environment. In this paper, we propose a restaurant recommender system in mobile environment. This recommender system adopts a user preference model by using the features of user's visited restaurants, and also utilizes the location information of user and restaurants to dynamically generate the recommendation results. Baidu map cloud service is used to implement the proposed recommender system. The result of a case study shows that the proposed restaurant recommender system can effectively utilize user's preference and the location information to recommend the personalized and suitable restaurants for different users.

关键词： Recommender systems Mobile communication Servers Mobile handsets Context Semantics Analytical models

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Learning Robust Travel Preferences Via Check-In Masking for Next Poi Recommendation

SSRN

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SSRN 2023年

作者： Duan, Chenghua Zhou, Wei Zeng, Jun Zhang, Yihao Wen, Junhao School of Bigdata and Software Engineering Chongqing University Daxuecheng South Rd. 55 Chognqing400044 China Key Laboratory of Dependable Service Computing in Cyber Physical Society Moe Chognqing400044 China School of Artificial Intelligence Chongqing University of Technology Chognqing401135 China

Next point-of-interest (POI) recommendation is a crucial part of many location-based service applications. It predicts users’ next visit based on their historical trajectories and current *** solutions primarily focus on sequential modeling of users’ check-in behavior. Unfortunately, most current research overlooks the fact that check-ins are implicit feedback, and inherent noise exists within them. To this end, we propose an approach to cope with noise-learning robust user travel preferences. Specifically, we design a masking strategy for check-ins, which masks the spatio-temporal information of some check-ins in users’ trajectories and forces our model to learn visit preferences without relying on individual inputs, thereby mitigating the bias caused by noisy check-ins. Then, we utilize multi-level geographical information to recommend the next POI more accurately. Additionally, we propose another masking strategy that considers users’ living area and automatically selects the proper strategy based on trajectory features. To the best of our knowledge, this is the first work that investigates the characteristics of noisy check-ins and performs denoising in next POI recommendation. Through extensive experiments, we demonstrate that our model outperforms state-of-the-art approaches and effectively handles data sparsity and noise issues. © 2023, The Authors. All rights reserved.

关键词： Trajectories

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RESTful web service composition: Extracting a process model from Linear Logic theorem proving

RESTful web service composition: Extracting a process model ...

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International Conference on Next Generation Web services Practices (NWeSP)

作者： Xia Zhao Enjie Liu Gordon J. Clapworthy Na Ye Yueming Lu Department of Computer Science and Technology University of Bedfordshire Luton UK School of Electronic and Information Engineering Xi'an Jiaotong University Xian China School of Information and Control Engineering Xi'an University of architecture and technology Xian China Key Laboratory of Trustworthy Distributed Computing and Service Ministry of Education Beijing University of Posts and Telecommunications Beijing China

This paper introduces a two-stage Linear Logic based program synthesis approach to automatic RESTful web service composition. The Linear Logic theorem proof is applied at both resource and service invocation method levels, which greatly improves the searching efficiency and guarantees the correctness and completeness of the service composition. Furthermore, the process calculus is used as formalism for the composition process, which enables the approach to be executable at the business management level. The process calculus is attached to the Linear Logic inference rules in the style of type theory, so the process model is extracted directly from the complete proof. An example is given to show the extraction of a process model from a Linear Logic proof search.

关键词： Web services Business Calculus Educational institutions Next generation networking Marine vehicles Electronic mail

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Tradeoff cache between latency and capacity in chip multiprocessors

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Jisuanji Yanjiu yu Fazhan/Computer Research and Development 2009年第1期46卷 167-175页

作者： Xiao, Junhua Feng, Zijun Zhang, Longbing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate School Chinese Academy of Sciences Beijing 100049 China

Chip multiprocessors (CMP) have become the main stream microprocessor architecture. In CMP, the cache, especially the last level cache, is the critical part of its performance and becomes a focus of current research activities. CMP cache faces the conflicting requirements of satisfying both latency and capacity, and has to trade off between techniques that reduce off-chip and cross-chip misses. The private cache design minimizes the cache access latency but reduces the total effective cache capacity. The shared cache design maximizes the effective cache capacity but incurs long hit latency. In this paper, a CMP cache design (tradeoff cache between latency and capacity, TCLC) is proposed. TCLC is a private and shared hybrid design. TCLC can dynamically identify the cache blocks' shared type and optimize them respectively. The private type is optimized through migration policy, the shared read-only type is optimized through replication policy, and the shared read-write type is optimized through center placement policy. TCLC tries to make cache access latency close to private design, and effective cache capacity close to shared design, which can mitigate the impact of the wire delay and reduce the average memory access latency. The experiment results indicate that this proposal performs 13.7% better than a private cache and 12% better than a shared cache.

关键词： Economic and social effects

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An optimal multicast-based testing algorithm for hotspot avoidance in NoC-based many-core chips

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Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of technology 2009年第SUPPL. 1期41卷 166-171页

作者： Fang, Fang Wang, Wei Han, Yin-He Li, Xiao-Wei Hefei University of Technology Hefei 230009 China System Architecture Key Laboratory Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

When many-core chips based on Network-on-chip (NoC) are under test, test time can be much reduced by using multicasting communication as data transmission technology and achieving parallel testing of many identical cores. However, it may have high power density and cause hotspot in test, which can exacerbate crosstalk and delay problems. In this paper, we present an optimal multicast-based testing algorithm for hotspot avoidance by generating multicasting test paths. Considering the thermal factor, we further investigate the paths, analyze the reason of hotspot and the effect of cores' distribution on hotspot, and propose a multicasting paths optimization strategy which is designed to avoid hotspot within identical cores. Experimental results show that the temperature of the many-core chip can be restricted and hotspots can be avoided efficiently.

关键词： Network-on-chip

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Physical-annotation-based power modeling and estimation method for processor

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics 2007年第11期19卷 1471-1475页

作者： Huang, Kun Zhang, Ge Wang, Jun Zeng, Hongbo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation, and all kinds of processor modules are mapped into combinations of basic components. Those models are linked to an architectural simulator, running benchmarks to get power results. The power analysis of benchmark platforms proves to be effective and highly correlated, with an average 10% error and little speed penalty compared with the gate-level power analysis.

关键词： High performance processor Physical annotation Power estimation Power modeling

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Cache adaptive write allocate policy

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Jisuanji Yanjiu yu Fazhan/Computer Research and Development 2007年第2期44卷 348-354页

作者： Huan, Dandan Li, Zusong Hu, Weiwu Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. The cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Compared with other cache store miss policies, the cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases load and store queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing the cache adaptive write allocate policy. The performance of SPEC CPU 2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.

关键词： Microprocessor chips

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Register pressure sensitive instruction speculative scheduling technology

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Jisuanji Yanjiu yu Fazhan/Computer Research and Development 2009年第3期46卷 485-491页

作者： Huang, Lei Feng, Xiaobing Lü, Fang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Speculation is an important method to overcome control flow constraints during instruction scheduling. On the one hand, speculation can exploit more instruction-level parallelism and improve performance. However, on the other hand, it may also lengthen the live range of variables and increase the register pressure, which in turn results in spilling some variables to memory and deteriorating the performance. Previous work on register pressure sensitive instruction scheduling generally scheduled instructions conservatively when there were too many live variables in the scheduling region. But actually different variables have different spilling costs and different impacts on performance. Here a register pressure sensitive speculative instruction scheduling technology is presented, which not only considers the count of live variables, but also analyzes the benefits and the spilling costs brought by instructions' speculative motions. The decrement of cycles in critical path is calculated as benefit, while the spilled variables are predicted and their spilling cost is used as cost. Only the speculative motion with benefit greater than the cost is permitted in our method. This algorithm has been implemented in Godson Compiler for MIPS architecture. Experiment result shows that the method in this paper can obtain 1.44% speedup on average relative to its register pressure insensitive counterpart on SPEC CPU2000INT benchmarks.

关键词： Costs

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Study on blocked LU decomposition on many-core architecture

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Gaojishu Tongxin/Chinese High technology Letters 2011年第3期21卷 248-253页

作者： Yu, Lei Liu, Zhiyong Ma, Yike Song, Fenglong Xu, Weizhi Ye, Xiaochun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

The authors studied the scientific application LU decomposition deeply. A speedup model for LU decomposition was proposed, and an algorithm for LU decomposition based on bit reverse xor (BRX) was implemented. Then a dynamic absolute balance policy (DABP) algorithm was presented. In order to estimate the algorithms of 2 dimensional (2D) scatter, BRX and DABP, two different estimation functions were given and they were used to estimate the load balance problem of the algorithms. These two functions verify that the DABP algorithm has the best load balance. The simulations of the three algorithms were performed on the many-core architecture Godson-T. The experiments prove that the speedup of the DABP algorithm is 46 and it is the best performance of the three algorithms.

关键词： Computer architecture

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Dependability evaluation system based on microprocessor function model

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Jisuanji Xuebao/Chinese Journal of Computers 2008年第3期31卷 391-399页

作者： Zhang, Shi-Jian Xu, Tong Zhang, Long-Bing Hu, Wei-Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100039 China

With the widespread adoption of embedded microprocessor-based systems in safety critical applications, such as aircrafts, spaceships and nuclear power plants, how to rapidly and conveniently evaluate these fault-tolerant mechanisms with low cost is an important problem. The traditional method requires a detailed hardware protocol to do evaluation, which lengthens evaluation period and increases the cost. A new dependability evaluation technique based on microprocessor function model is proposed, which can evaluate fault-tolerant mechanisms more rapidly, more conveniently and more economically than the conventional systems. As a case for study, the new system evaluates three fault-tolerant techniques;the software redundancy technique, the assertion validation technique and the instruction re-fetching and re-execution technique. The results show that the evaluation is reasonable.

关键词： Fault tolerance

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