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Coverage optimization in wireless mobile sensor networks

Coverage optimization in wireless mobile sensor networks

引用

5th International Conference on Wireless Communications, Networking and Mobile computing, WiCOM 2009

作者： Xingzhen, Bai Shu, Li Changjun, Jiang Zhengzhong, Gao Electronics and Information Engineering School Tongji University Shanghai 201804 China Key Laboratory for the Embedded System and Service Computing of Ministry of Education Tongji University Shanghai 201804 China College of Information and Electrical Engineering Shandong University of Science and Technology Qingdao 266510 China

ISBN: (纸本)9781424436934

The coverage of Wireless Sensor Networks (WSNs) is one of the most important measurement criteria of Qos. Optimal coverage of sensors is propitious to the maximum possible utilization of the available sensors. It can balance node energy consumption, and elongate network lifetime. In this paper, particle swarm optimization (PSO) approach is applied to maximize the coverage of mobile sensor networks. We first analyze the node distribution of random deployed sensor networks. There are big coverage holes as the network size grows. In order to reduce energy consumption during node move process, we study the sensor network coverage optimization in the limited mobility model. The simulation results show that sensor node move in the limited region can also realize the coverage optimization , and it can reduce the moving distance greatly. ©2009 IEEE.

关键词： Sensor nodes

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An efficient methodology for power modeling and simulation of modern cell-based microprocessors

An efficient methodology for power modeling and simulation o...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： Ge Zhang Weiwu Hu Institute of Computing Technology Key Laboratory of Computer System and Architecture Beijing China

This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given processor, is developed and annotated dynamically for architecture-level power simulator. According to this method, the dynamic power, leakage power and even area and cell counts can be accurately estimated, and the preliminary power validation for a MIPS microprocessor proves our methodology to be effective and highly correlated, with only small errors comparing with the gate-level power analysis.

关键词： Microprocessors Circuit simulation Libraries Adders Circuit synthesis Power system modeling Analytical models Content addressable storage Power generation Flexible printed circuits

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Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

引用

18th Asian Test Symposium, ATS 2009

作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China

ISBN: (纸本)9780769538648

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding. © 2009 IEEE.

关键词： Filling

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HPPNetSim: A parallel simulation of large-scale interconnection networks

HPPNetSim: A parallel simulation of large-scale interconnect...

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42nd Annual Simulation Symposium 2009, ANSS 2009, Part of the 2009 Spring Simulation Multiconference

作者： Cao, Zheng Xu, Jianwei Chen, Mingyu Zheng, Gui Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781617386404

As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel interconnection network simulator is a suitable tool to study large-scale interconnection networks. However, simulating packet level communication on detailed cycle-to-cycle network models is a really challenge work. We implement a kernel-based parallel simulator HPPNetSim to solve problems. Optimistic PDES mechanism needs huge memory consumption of saving simulation entities' states in large-scale simulations, so we chose conservative synchronization approach. Simulation kernel and network models are all carefully designed. To accelerate process of simulation, optimizations are introduced, such as block/unblock synchronization, load balancing, dynamic look-ahead generation, and etc. Simulation examples and performance results show that both high accuracy and good performance are obtained in HPPNetSim. It achieves speedup of 19.8 for 32 processing nodes when simulating 36-port 3-tree fat-tree network.

关键词： Discrete event simulation

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A case study of improving at-speed testing coverage of a gigahertz microprocessor

A case study of improving at-speed testing coverage of a gig...

引用

2009 16th IEEE International Conference on Electronics, Circuits and systems, ICECS 2009

作者： Qi, Zichu Liu, Hui Li, Xiangku Xu, Jun Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences PO Box 2704-25 Beijing 100190 China Beijing China Loongson Technologies Corporation Limited China

ISBN: (纸本)9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (Random Access Memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improv. The efficiency oy the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By usin. The flow, 90% transition fault coverage is achieved. In addition, bot. The number of patterns an. The test time oy the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact oy the critical paths. © 2009 IEEE.

关键词： Random access storage

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Improved Extremal Optimization for Constrained Pairwise Testing

Improved Extremal Optimization for Constrained Pairwise Test...

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International Conference on Research Challenges in Computer Science (ICRCCS)

作者： Jianjun Yuan Changjun Jiang Zuowen Jiang Department of Computer Science and Technology The Key Laboratory of Embedded System and Service Computing Ministry of Education of China University of Tongji Shanghai China

Pairwise testing, which requires that every combination of valid values of each pair of system factors be covered by at lease one test case, plays an important role in software testing since many faults are caused by unexpected 2-way interactions among system factors. In real systems, constraints usually exist between values, which means that some values cannot coexist in a valid test. Although meta-heuristic strategies like simulated annealing can generally discover smaller pairwise test suite in the presence of constraints, they may cost more time to perform search, compared with greedy algorithms. We propose a new method, improved extremal optimization, for constructing constrained pairwise test suites. Experimental results show that improved extremal optimization gives similar size of resulting pairwise test suite and yields a 13% reduction in solution time over simulated annealing.

关键词： Constraint optimization Software testing system testing Simulated annealing Costs Greedy algorithms Computer science Educational technology Laboratories Embedded system

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HPPNetSim: A parallel simulation of large-scale interconnection networks

HPPNetSim: A parallel simulation of large-scale interconnect...

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2009 Spring Simulation Multiconference, SpringSim 2009

作者： Cao, Zheng Xu, Jianwei Chen, Mingyu Gui, Zheng Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel interconnection network simulator is a suitable tool to study large-scale in-terconnection networks. However, simulating packet level communication on detailed cycle-to-cycle network models is a really challenge work. We implement a kernel-based parallel simulator HPPNetSim to solve problems. Optimistic PDES mechanism needs huge memory consumption of sav-ing simulation entities' states in large-scale simulations, so we chose conservative synchronization approach. Simula-tion kernel and network models are all carefully designed. To accelerate process of simulation, optimizations are in-troduced, such as block/unblock synchronization, load balancing, dynamic look-ahead generation, and etc. Simula-tion examples and performance results show that both high accuracy and good performance are obtained in HPPNetSim. It achieves speedup of 19.8 for 32 processing nodes when simulating 36-port 3-tree fat-tree network.

关键词： Discrete event simulation

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Study on stability of traffic flow for cooperative driving control

Study on stability of traffic flow for cooperative driving c...

引用

IEEE Symposium on Intelligent Vehicle

作者： Zhipeng Li Ping Wang Fuqiang Liu Key Laboratory of Embedded System and ServIce Computing supported by Ministry of Education University of Tongji Shanghai China

ISBN: (纸本)9781424435036

In the literature of traffic flow theory, the research on the effect on stability of traffic flow for cooperative driving control possesses an important significance. However, presently the the study on the problem is unsatisfactory because it is difficult to determine the impact qualitatively or quantitatively in real traffic experiment. In this paper, some efforts have been made for better understanding the effect on stability of traffic flow for cooperative driving control by investigating the stability for lattice traffic models, which are presented here by incorporating motion information of cars preceding. From linear stability analysis and direct simulations validation, we learn some properties of the effect on the stability and congestion waves by using the information of many other cars. First, cooperative driving behavior of many cars preceding can efficiently stabilize the traffic flow. Second, cooperative driving behavior of the cars nearby plays a prominent role in stability. Third, when the car number participating in cooperative driving policy exceeds a certain value, the congestion waves will disappear.

关键词： Traffic control Control systems Communication system traffic control Roads Laboratories Embedded system Embedded computing Stability analysis Transportation Mathematical model

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A New Post-Silicon Debug Approach Based on Suspect Window

A New Post-Silicon Debug Approach Based on Suspect Window

引用

IEEE VLSI Test Symposium (VTS)

作者： Jianliang Gao Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.

关键词： Post-silicon debug Suspect window Trace Scan Bug

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Adaptation of Mismatching services Based on Labelled Interface Automata

Adaptation of Mismatching Services Based on Labelled Interfa...

引用

Fifth International Conference on Semantics,Knowledge and Grid(第五届语义、知识与网格国际会议 SKG 2009)

作者： Tao Liu Guosun Zeng Department of Computer Science and Technology Tongji University Shanghai 200092 China The Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji Universit

In today's web, more and more software and applications are wrapped as services. However interactions between services are not always perfectly completed because of mismatches among them. service mediation and adaptation problems obtain increasingly concerns. In this paper, we propose an extension of interface automata, labelled interface automata, to illustrate mismatching services and adaptation. We characterize the problem by classifying different kinds of adaptation scenarios. Then we focus on how to use labelled interface automata to illustrate the building of adaption service between mismatching services.

关键词： mismatching service adaptation interface automata

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