检索结果-内蒙古大学图书馆

Joint 30th International Conference on Computational Linguistics and 14th International Conference on Language Resources and Evaluation, LREC-COLING 2024

作者： Wang, Quan Zhang, Licheng Guo, Zikang Mao, Zhendong MOE Key Laboratory of Trustworthy Distributed Computing and Service Beijing University of Posts and Telecommunications Beijing China University of Science and Technology of China Hefei China

ISBN: (纸本)9782493814104

The effective detection of AI-generated text is a vital principle to ensure responsible use of large language models (LLMs). Previous studies mainly focused on discovering and utilizing internal evidences contained in the text itself to perform the detection, while ignoring external evidences implicated in an established knowledge graph (KG) which may also be key discriminative factors between AI-generated and human-written text. To address this deficiency, we propose IDEATE, a novel hierarchical graph network that utilizes both internal and external factual structures to detect AI-generated text. IDEATE consists of a mention-level subgraph at the bottom to describe internal factual structures of mentioned entities reflected in the input text, and an entity-level subgraph at the top to describe external factual structures of mentioned entities reflected in an external KG. Hierarchical graph convolution is then applied successively on the two subgraphs, through which the two types of factual structures will be embedded into the output and used for the final detection. Extensive experiments on four benchmarking datasets show that IDEATE consistently outperforms current state-of-the-art methods in detecting text generated by various LLMs, ranging from GPT-2 to the more powerful ChatGPT, verifying the necessity and superiority of introducing external evidences for AI-generated text detection. © 2024 ELRA Language Resource Association: CC BY-NC 4.0.

关键词： Knowledge graph

来源：评论

学校读者我要写书评

暂无评论

Address remapping for static NUCA in noc-based degradable chip-multiprocessors

Address remapping for static NUCA in noc-based degradable ch...

引用

16th IEEE Pacific Rim International Symposium on Dependable computing, PRDC 2010

作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542898

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme. © 2010 IEEE.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

引用

2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Hu, Yu Fu, Xiang Fan, Xiaoxin Fujiwara, Hideo Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China 8916-5 Takayama Ikoma Nara 630-0192 Japan

ISBN: (纸本)9781424419227

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead. ©2008 IEEE.

关键词： Multiplexing equipment

来源：评论

学校读者我要写书评

暂无评论

Diva: A dataflow programming model and its runtime support in java virtual machine

Diva: A dataflow programming model and its runtime support i...

引用

13th IEEE Asia-Pacific Computer systems Architecture Conference, ACSAC 2008

作者： Yang, Chen Bin, Fan Lujie, Zhong Chengyong, Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate School of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424426836

Microprocessors have turned to multicore, i.e. multiple processor cores, along with some levels of on-chip caches and interconnection networks, integrated on a singe chip. However, it brings challenges on how to program these processors effectively and efficiently, which is known as the "Programming Wall". This paper proposes a systematic approach to attack the problem. We describe an extension of Java programming language with dataflow paradigm and transactional memory. Our approach alleviates the difficulties of parallel programming by providing a higher level of abstraction and relieving programmers of low-level threading and locking details. We also describe the design of a runtime system to support and optimize for the extension. We have implemented a prototype based on Apache Harmony DRL Virtual Machine. Preliminary experimental results on a 16-core SMP machine show that our approach achieves reasonable scalability and can adapt to the variance of available hardware resources. © 2008 IEEE.

关键词： Parallel programming

来源：评论

学校读者我要写书评

暂无评论

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

引用

2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Wang, Fei Hu, Yu Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424419227

The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique. ©2008 IEEE.

关键词： Chains

来源：评论

学校读者我要写书评

暂无评论

Design of new hash mapping functions

Design of new hash mapping functions

引用

IEEE 9th International Conference on Computer and Information technology, CIT 2009

作者： Song, Fenglong Liu, Zhiyong Fan, Dongrui Zhang, Junchao Yu, Lei Yuan, Nan Lin, Wei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflictfree. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewedassociative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme. © 2009 IEEE.

关键词： Hash functions

来源：评论

学校读者我要写书评

暂无评论

A microscopic view on community detection in complex networks

A microscopic view on community detection in complex network...

引用

2nd PhD Workshop on Information and Knowledge Management, PIKM'08, Co-located with the 17th ACM Conference on Information and Knowledge Management, CIKM'08

作者： Wang, Yang Song, Huaiming Wang, Weiping An, Mingyuan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781605583877

The community structure is a basic characteristic of complex networks. A strong community structure has high modularity. It has been proven an NP-Complete problem to identify the community structure with the highest modularity. Many approximate algorithms have been proposed to alleviate the problem. However, they suffer from inefficiency or low quality. In this paper, we propose a two-step method. The first step of our method analyze the vertex similarity of the network, which is a microscopic view. If a pair of vertices are similar enough, they will be put into the same community. The second step of our method focuses on the increment of modularity of the similarity-based communities generated by the first step. If the number of edges between two communities is greater than the expected number based on random choice, the two communities will be merged. The second step is implemented by the CNM algorithm or its improvement CNM+HE'. The similarity-based community remedies the defect on microscope introduced by CNM or CNM+HE'. Our method runs efficiently and finds meaningful communities effectively. We tested the method on more than twenty datasets. The modularity of community structure found by the method is higher than the state-of-the-art algorithm. Copyright 2008 ACM.

关键词： Complex networks

来源：评论

学校读者我要写书评

暂无评论

A low overhead on-chip path delay measurement circuit

A low overhead on-chip path delay measurement circuit

引用

18th Asian Test Symposium, ATS 2009

作者： Pei, Songwei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Academy of Sciences Graduate University of Chinese Beijing 100190 China

ISBN: (纸本)9780769538648

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy. © 2009 IEEE.

关键词： Timing circuits

来源：评论

学校读者我要写书评

暂无评论

Multi-tiered on-demand resource scheduling for VM-based data center 09

Multi-tiered on-demand resource scheduling for VM-based data...

引用

2009 9th IEEE/ACM International Symposium on Cluster computing and the Grid, CCGRID 2009

作者： Song, Ying Wang, Hui Yaqiong, Li Feng, Binquan Sun, Yuzhong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769536224

The trend of using virtualization for server consolidation is more and more popular in enterprise data center. However, ondemand resource allocation among the concurrent hosted services in such a virtualized environment is still a challenge. In order to optimize resource allocation among services in data center, this paper proposes a multi-tiered resource scheduling scheme which automatically provides on-demand capacities to the hosted services via resources flowing among VMs. We model the resource flowing using optimization theory. Based on this model, we present a global resource flowing algorithm in the multi-tiered resource scheduling scheme. This algorithm preferentially ensures performance of some critical services by degrading of others to some extent when resource competition arises. Using our RAINBOW prototype, we evaluate the multitiered resource scheduling scheme with the performance improvements for the most critical services up to 9%˜16%, which are 75% of the maximum improvement margin, while performance degradation of others is up to 2%, and leads to 1%˜5% improvements in resource utilization than RAINBOW without resource flowing. Compared with the existent scheme, our work leads to 9% less improvements for critical services, while introduces 39% less degradation to low priority services. © 2009 IEEE.

关键词： Resource allocation

来源：评论

学校读者我要写书评

暂无评论

Task allocation for maximizing reliability of distributed computing systems using honeybee mating optimization

引用

Journal of systems and Software 2010年第11期83卷 2165-2174页

作者： Kang, Qin-Ma He, Hong Song, Hui-Min Deng, Rong Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 201804 China School of Information Engineering Shandong University at Weihai 180 Wenhua Xilu Weihai 264209 China School of Mathematics and Statistics Shandong University at Weihai Weihai 264209 China

This paper deals with the problem of task allocation (i.e,;to which processor should each task of an application be assigned) in heterogeneous distributed computing systems with the goal of maximizing the system reliability. The problem of finding an optimal task allocation is known to be NP-hard in the strong sense. We propose a new swarm intelligence technique based on the honeybee mating optimization (HBMO) algorithm for this problem. The HBMO based approach combines the power of simulated annealing, genetic algorithms with a fast problem specific local search heuristic to find the best possible solution within a reasonable computation time. We study the performance of the algorithm over a wide range of parameters such as the number of tasks, the number of processors, the ratio of average communication time to average computation time, and task interaction density of applications. The effectiveness and efficiency of our algorithm are demonstrated by comparing it with recently proposed task allocation algorithms for maximizing system reliability available in the literature. © 2010 Elsevier Inc. All rights reserved.

关键词： Reliability

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：