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The 9th International Conference for Young Computer Scientists(第九届国际青年计算机大会)

作者： Ge Cheng Hai Jin Deqing Zou Alex K. Ohoussou Feng Zhao Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China

In virtual machine (VM) systems, mandatory access control (MAC) enforcement is possible now. This technique is both stronger and more flexible than traditional VM isolation, even if network communication is controlled. Unfortunately all of the VM systems with the MAC enforcement does not consider that the MAC controls may be distorted by covert channels, which constitute an important risk in VM systems. Traditional MAC models have difficulties being enforced to reduce the risk of covert flows in VM systems due to the many constraints and the lack of flexibility. In this paper, we identify access control requirements for managing covert channels in VM systems through a critical analysis of the ways by which classical models constrain the covert information flows and we propose a model called the Prioritized Chinese Wall model (PCW) to reduce the risk of covert flows in VM systems while preserving the flexibility. Furthermore, we enforce the policy in sHype/Xen VM system.

关键词： Information management Virtual machining Virtual manufacturing Communication system control Control systems Risk management Access control Hardware Grid computing Isolation technology

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Echo: An Edge-Centric Code Offloading system with Quality of service Guarantee

arXiv

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arXiv 2018年

作者： Lin, Li Liao, Xiaofei Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

Code offloading is promising to accelerate mobile applications and save energy of mobile devices by shifting some computation to cloud. However, existing code offloading systems suffer from a long communication delay between mobile devices and cloud. To address this challenge, in this paper, we consider to deploy edge nodes in the proximity of mobile devices, and study how they benefit code offloading. We design an edge-centric code offloading system, called Echo, over a three-layer computing hierarchy consisting of mobile devices, edge and cloud. A critical problem needs to be addressed by Echo is to decide which method should be offloaded to which computing platform (edge or cloud). Different from existing offloading systems that let mobile devices individually make offloading decisions, Echo implements a centralized decision engine at the edge node. This edge-centric design can fully exploit the limited hardware resources at the edge to provide an offloading service with Quality of service guarantee. Furthermore, we propose some novel mechanisms, e.g., lazy object transmission and differential object update, to further improve system performance. The results of a small-scale real deployment and trace-driven simulations show that Echo significantly outperforms existing code offloading systems at both execution time and energy consumption. Copyright © 2018, The Authors. All rights reserved.

关键词： Edge computing

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Transactional Memory Consistency : A New Consistency Model for Distributed Transactional Memory

Transactional Memory Consistency : A New Consistency Model f...

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The Third International Joint Conference on Computational Science and Optimization(第三届计算科学与优化国际大会 CSO 2010)

作者： Xuping Tu Xuepeng Fan Hai Jin Long Zheng Xin Peng Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China

Transactional memory (TM) is a parallel programming concept. Existing consistency protocols in distributed transactional memory system consume too much bandwidth and bring high latency. In this paper, we propose our Transaction Memory Consistency Protocol (TMCP), and point the new features compared to the current protocols. After formulating our model and analyzing the performance, we found both too much and too little execution time will cause more conflicts, given that the execution time of transaction population follows Gamma distribution. We indicate that it is important to adjust the execution time to a reasonable value to improve performance.

关键词： distributed system distributed shared memory software transactional memory consistency model

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PBJIM: Plugin-based Job Interoperation Mechanism for Heterogeneous Grid systems

PBJIM: Plugin-based Job Interoperation Mechanism for Heterog...

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第六届网格与协同计算国际会议(The Sixth International Conference on Grid and Cooperative computing GCC 2007)

作者： Song Wu Yongcai Tao Zhongqing Xu Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China

With the development of grid technology, grid gains more popularity that ever and a variety of grid middlewares come into being. However, most of grid middlewares are developed by their own, and it's not easy to interoperate these grid platforms. Existing grid interoperability projects mainly resorts to case-by-case mechanism, which is simple but of poor scalability. Job management is the core and the most complex components of grid system. To realize the interoperability of heterogeneous grids, the interoperation of heterogeneous job managements must be addressed In the paper, a plugin based job interoperation mechanism for heterogeneous grid systems, called PBJIM, is proposed, which is based on the idea of virtualization and plug-in *** are two well-established grid systems in China,ChinaGrid and China National Grid, and they are built with two different grid middlewares, CGSP and VEGA. Via PBJIM, the interoperation of job management of these two grid systems is achieved.

关键词： Middleware Grid computing Information management Identity management systems Computer science Scalability Standards development Data security Information security Management information systems

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Spara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications

Spara: An Energy-Efficient ReRAM-Based Accelerator for Spars...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Long Zheng Jieshan Zhao Yu Huang Qinggang Wang Zhen Zeng Jingling Xue Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Resistive random access memory (ReRAM) addresses the high memory bandwidth requirement challenge of graph analytics by integrating the computing logic in the memory. Due to the matrix-structured crossbar architecture, existing ReRAM-based accelerators, when handling real-world graphs that often have the skewed degree distribution, suffer from the severe sparsity problem arising from zero fillings and activation nondeterminism, incurring substantial ineffectual *** this paper, we observe that the sparsity sources lie in the consecutive mapping of source and destination vertex index onto the wordline and bitline of a crossbar. Although exhaustive graph reordering improves the sparsity-induced inefficiency, its totally-random (source and destination) vertex mapping leads to expensive overheads. This work exploits the insight in a mid-point vertex mapping with the random wordlines and consecutive bitlines. A cost-effective preprocessing is proposed to exploit the insight by rapidly exploring the crossbar-fit vertex reorderings but ignores the sparsity arising from activation dynamics. We present a novel ReRAM-based graph analytics accelerator, named Spara, which can maximize the workload density of crossbars dynamically by using a tightly-coupled bank parallel architecture further proposed. Results on real-world and synthesized graphs show that Spara outperforms GraphR and GraphSAR by 8.21 × and 5.01 × in terms of performance, and by 8.97 × and 5.68× in terms of energy savings (on average), while incurring a reasonable (

关键词： Indexes Electrodes Random access memory Parallel architectures Resistance Memory management

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A Heterogeneous PIM Hardware-Software Co-Design for Energy-Efficient Graph Processing

A Heterogeneous PIM Hardware-Software Co-Design for Energy-E...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Yu Huang Long Zheng Pengcheng Yao Jieshan Zhao Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Processing-In-Memory (PIM) is an emerging technology that addresses the memory bottleneck of graph processing. In general, analog memristor-based PIM promises high parallelism provided that the underlying matrix-structured crossbar can be fully utilized while digital CMOS-based PIM has a faster single-edge execution but its parallelism can be low. In this paper, we observe that there is no absolute winner between these two representative PIM technologies for graph applications, which often exhibit irregular workloads. To reap the best of both worlds, we introduce a new heterogeneous PIM hardware, called Hetraph, to facilitate energy-efficient graph processing. Hetraph incorporates memristor-based analog computation units (for high-parallelism computing) and CMOS-based digital computation cores (for efficient computing) on the same logic layer of a 3D die-stacked memory device. To maximize the hardware utilization, our software design offers a hardware heterogeneity-aware execution model and a workload offloading mechanism. For performance speedups, such a hardware-software co-design outperforms the state-of-the-art by 7.54 ×(CPU), 1.56 ×(GPU), 4.13× (memristor-based PIM) and 3.05× (CMOS-based PIM), on average. For energy savings, Hetraph reduces the energy consumption by 57.58× (CPU), 19.93× (GPU), 14.02 ×(memristor-based PIM) and 10.48 ×(CMOS-based PIM), on average.

关键词： Hardware Computer architecture Parallel processing Three-dimensional displays Computational modeling Graphics processing units Memristors

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SumPA: Efficient Pattern-Centric Graph Mining with Pattern Abstraction 21

SumPA: Efficient Pattern-Centric Graph Mining with Pattern A...

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Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques

作者： Chuangyi Gui Xiaofei Liao Long Zheng Pengcheng Yao Qinggang Wang Hai Jin National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9781665442787

Graph mining aims to explore interesting structural information of a graph. Pattern-centric systems typically transform a generic-purpose graph mining problem into a series of subgraph matching problems for high performance. Existing pattern-centric mining systems reduce the substantial search space towards a single pattern by exploring a highly-optimized matching order, but inherent computational redundancies of such a matching order itself still suffer severely, leading to significant performance degradation. The key innovation of this work lies in a general redundancy criterion that characterizes computational redundancies arising in not only handing a single pattern but also matching multiple patterns simultaneously. In this paper, we present SumPA, a high-performance pattern-centric graph mining system that can sufficiently remove redundant computations for any complex graph mining problems. SumPA features three key designs: (1) a pattern abstraction technique that can simplify numerous complex patterns into a few simple abstract patterns based on pattern similarity, (2) abstraction-guided pattern matching that completely eliminates (totally and partially) redundant computations during subgraph enumeration, and (3) a suite of system optimizations to maximize storage and computation efficiency. Our evaluation on a wide variety of real-world graphs shows that SumPA outperforms the two state-of-the-art systems Peregrine and GraphPi by up to 61.89× and 8.94×, respectively. For many mining problems on large graphs, Peregrine takes hours or even days while SumPA finishes in only a few minutes.

关键词： data reuse

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Research on Architecture of Grid-Based Simulation Platform

Research on Architecture of Grid-Based Simulation Platform

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Japan-China Joint Workshop on Frontier of Computer Science and technology (FCST)

作者： Song Wu Li Qi Hai Jin Heng He Key Lab of Cluster and Grid Computing Key Lab of Service Computing Technology and System Ministry of Education Huazhong University of Science and Technology Wuhan Hubei China

This paper proposes a Grid-based Distributed Simulation Platform (GDSP). It is designed to break the limitation of legacy simulation supporting platform and to meet new requirements from large-scale, distributed, and complicated systems. Simulation services are encapsulated by using web services technology, and they are basic elements of GDSP. With grid technology, GDSP enables users to share, access, and operate remote resource transparently. It is also easier to organize and manage simulation resources. GDSP improves the capability of fault tolerance and provides mechanism of using simulation resources securely. The research result shows that through this management mechanism, multiple users can share and monitor RTI resources, and manage the simulation collaboratively and effectively. At the same time, the impact on real time of RTI caused by the system is minimum.

关键词： Computational modeling Resource management Web services Computer architecture Application software Large-scale systems Fault tolerance Distributed computing Context modeling Runtime

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LaLDPC: Latency-aware LDPC for read performance improvement of solid state drives 33

LaLDPC: Latency-aware LDPC for read performance improvement ...

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33rd International Conference on Massive Storage systems and technology, MSST 2017

作者： Du, Yajuan Zou, Deqing Li, Qiao Shi, Liang Jin, Hai Xuey, Chun Jason Service Computing Technology and System Lab Cluster and Grid Computing Lab Big Data Technol. and Syst. Lab Sch. of Comp. Sci. and Technology Huazhong Univ. of Sci. and Technol. Wuhan430074 China Department of Computer Science City University of Hong Kong Kowloon Hong Kong College of Computer Science Chongqing University Chongqing China

High-density Solid State Drives (SSDs) have to use Low-Density Parity-Check (LDPC) codes to store data reliably. Current LDPC implementations apply multiple read-retry steps to find the appropriate set of multiple Reference Voltage (RVs) for successful decoding. These appropriate RVs, number of which is represented by read level, cannot be obtained in advance, instead, an iterative read-retry LDPC process happens that starts with the first read level with the smallest number of RVs and then increases the level until that the data have been successfully decoded. Only read-retry with the last read level, called the appropriate read level, is necessary. Read latency can be improved by avoiding read-retries. This becomes particularly important in the late stage of SSD life when high read levels are needed. To avoid unnecessary read-retries, this paper proposes Latency-aware LDPC (LaLDPC). We study read level characteristics along with data retention and observe that a single read level stays appropriate for a long time. During this time, all reads in the same page have probably the same appropriate read level, which we call the temporal read level locality. Using this value, LaLDPC estimates the starting read voltage level, which we store in the flash translation layer of the controller. As an example, we show how to integrate LaLDPC into the Demand-based Flash Translation Layer (DFTL). A new cache eviction algorithm is also proposed to leave entries with high read levels in the cache as long as possible. Experimental results show that LaLDPC saves 56% of read retries and improves SSD read performance by 18% on average compared with the existing LDPC method. © 33rd International Conference on Massive Storage systems and technology, MSST 2017. All rights reserved.

关键词： Forward error correction

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Cost-Effective Resource Allocation in C-RAN with Mobile Cloud

Cost-Effective Resource Allocation in C-RAN with Mobile Clou...

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Ad-Hoc and Sensor Networks Symposium

作者： Kezhi Wang Kun Yang Xinhou Wang Chathura Sarathchandra Magurawalage School of Computer Sciences and Electrical Engineering University of Essex Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology

ISBN: (纸本)9781479966653

Taking full advantages of two cloud-based techniques, i.e., cloud radio access network (C-RAN) and mobile cloud computing (MCC), mobile operators will be able to provide the good service to the mobile user as well as increasing their revenue. This paper aims to minimize the mobile operator's cost while at the same time, meet the task time constraints of the mobile users. In particular, we assume that the mobile cloud first completes the tasks for the mobile user and then transmits the results back to the users through C-RAN. Joint cost-effective resource allocation is proposed between MCC and C-RAN and simulation results confirm that the proposed cost minimization and resource allocation solution outperforms non-optimal solutions.

关键词： C-RAN Cost-Effective Resource Allocation MCC

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