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Construct pairwise test suites based on the Bak-Sneppen model of biological evolution

World Academy of Science, Engineering and technology 2009年 35卷 224-229页

作者： Yuan, Jianjun Jiang, Changjun Department of Computer Science and Technology The Key Lab. of 'Embedded System and Service Computing' Ministry of Education of China Tongji University Shanghai 201804 China

Pairwise testing, which requires that every combination of valid values of each pair of system factors be covered by at lease one test case, plays an important role in software testing since many faults are caused by unexpected 2-way interactions among system factors. Although meta-heuristic strategies like simulated annealing can generally discover smaller pairwise test suite, they may cost more time to perform search, compared with greedy algorithms. We propose a new method, improved Extremal Optimization (EO) based on the Bak-Sneppen (BS) model of biological evolution, for constructing pairwise test suites and define fitness function according to the requirement of improved EO. Experimental results show that improved EO gives similar size of resulting pairwise test suite and yields an 85% reduction in solution time over SA.

关键词： Simulated annealing

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Superpage-Friendly Page Table Design for Hybrid Memory systems

Superpage-Friendly Page Table Design for Hybrid Memory Syste...

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2020国际计算机前沿大会

作者： Xiaoyuan Wang Haikun Liu Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System Huazhong University of Science and Technology Service Computing Technology and System Lab Huazhong University of Science and Technology Cluster and Grid Computing Lab Huazhong University of Science and Technology School of Computer Science and Technology Huazhong University of Science and Technology

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory(DRAM) and non-volatile memories(NVMs), to improve the system performance and energy ***, page migration introduces some side effects, such as more translation lookaside buffer(TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpagefriendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.

关键词： Pagetable Hybridmemorysystem Pagemigration Multiplepagesizes Addresstranslation

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Safe Reinforcement Learning with Dead-Ends Avoidance and Recovery

arXiv

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arXiv 2023年

作者： Zhang, Xiao Zhang, Hai Zhou, Hongtu Huang, Chang Zhang, Di Ye, Chen Zhao, Junqiao The Department of Computer Science and Technology Tongji University China The MOE Key Lab of Embedded System and Service Computing Tongji University China

Safety is one of the main challenges in applying reinforcement learning to realistic environmental tasks. To ensure safety during and after training process, existing methods tend to adopt overly conservative policy to avoid unsafe situations. However, overly conservative policy severely hinders the exploration, and makes the algorithms substantially less rewarding. In this paper, we propose a method to construct a boundary that discriminates safe and unsafe states. The boundary we construct is equivalent to distinguishing dead-end states, indicating the maximum extent to which safe exploration is guaranteed, and thus has minimum limitation on exploration. Similar to Recovery Reinforcement Learning, we utilize a decoupled RL framework to learn two policies, (1) a task policy that only considers improving the task performance, and (2) a recovery policy that maximizes safety. The recovery policy and a corresponding safety critic are pretrained on an offline dataset, in which the safety critic evaluates upper bound of safety in each state as awareness of environmental safety for the agent. During online training, a behavior correction mechanism is adopted, ensuring the agent to interact with the environment using safe actions only. Finally, experiments of continuous control tasks demonstrate that our approach has better task performance with less safety violations than state-of-the-art algorithms. Copyright © 2023, The Authors. All rights reserved.

关键词： Reinforcement learning

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Real-time action recognition with enhanced motion vector CNNs

Real-time action recognition with enhanced motion vector CNN...

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2016 IEEE Conference on Computer Vision and Pattern Recognition, CVPR 2016

作者： Zhang, Bowen Wang, Limin Wang, Zhe Qiao, Yu Wang, Hanli Shenzhen Key Lab of Comp. Vis. and Pat. Rec. Shenzhen Institutes of Advanced Technology CAS China Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai China Computer Vision Lab ETH Zurich Switzerland

ISBN: (纸本)9781467388511

The deep two-stream architecture [23] exhibited excellent performance on video based action recognition. The most computationally expensive step in this approach comes from the calculation of optical flow which prevents it to be real-time. This paper accelerates this architecture by replacing optical flow with motion vector which can be obtained directly from compressed videos without extra calculation. However, motion vector lacks fine structures, and contains noisy and inaccurate motion patterns, leading to the evident degradation of recognition performance. Our key insight for relieving this problem is that optical flow and motion vector are inherent correlated. Transferring the knowledge learned with optical flow CNN to motion vector CNN can significantly boost the performance of the latter. Specifically, we introduce three strategies for this, initialization transfer, supervision transfer and their combination. Experimental results show that our method achieves comparable recognition performance to the state-of-the-art, while our method can process 390.7 frames per second, which is 27 times faster than the original two-stream method.

关键词： Pattern recognition

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RAHP: A Redundancy-aware Accelerator for High-performance Hypergraph Neural Network

RAHP: A Redundancy-aware Accelerator for High-performance Hy...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Hui Yu Yu Zhang Ligang He Yingqi Zhao Xintao Li Ruida Xin Jin Zhao Xiaofei Liao Haikun Liu Bingsheng He Hai Jin National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Department of Computer Science University of Warwick United Kingdom National University of Singapore Singapore

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Hypergraph Neural Network (HyperGNN) has emerged as a potent methodology for dissecting intricate multilateral connections among various entities. Current software/hardware solutions leverage a sequential execution model that relies on hyperedge and vertex indices for conducting standard matrix operations for HyperGNN inference. Yet, they are impeded by the dual challenges of redundant computation and irregular memory access overheads. This is primarily due to the frequent and repetitive access and updating of a number of feature vectors corresponding to the same hyperedges and vertices. To address these challenges, we propose the first redundancy-aware accelerator, RAHP, which enables high performance execution of HyperGNN inference. Specifically, we present a redundancy-aware asynchronous execution approach into the accelerator design for HyperGNN to reduce redundant computations and off-chip memory accesses. To unveil opportunities for data reuse and unlock the parallelism that existing HyperGNN solutions fail to capture, it prioritizes vertices with the highest degree as roots, prefetching other vertices along the hypergraph structure to capture the common vertices among multiple hyperedges, and synchronizing the computations of hyperedges and vertices in real-time. By such means, this facilitates the concurrent processing of relevant hyperedge and vertex computations of the common vertices along the hypergraph topology, resulting in smaller redundant computations overhead. Furthermore, by efficiently caching intermediate results of the common vertices, it curtails memory traffic and off-chip communications. To fully harness the performance potential of our proposed approach in the accelerator, RAHP incorporates a topology-driven data loading mechanism to minimize off-chip memory accesses on the fly. It is also endowed with an adaptive data synchronization scheme to mitigate the effects of conflicting updates of both hyperedges and vertices. Moreover, RAHP emplo

关键词： Computational modeling Neural networks Memory management Loading Energy conservation Vectors Software Topology Synchronization Standards

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Accelerating GPGPU architecture simulation

Accelerating GPGPU architecture simulation

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2013 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer systems, SIGMETRICS 2013

作者： Yu, Zhibin Eeckhout, Lieven Goswami, Nilanjan Li, Tao John, Lizy K. Jin, Hai Xu, Chengzhong Shenzhen Institute of Advanced Technology Chinese Academy of Sciences China ELIS Department Ghent University Belgium Intelligent Design of Efficient Architectures Lab. University of Florida Gainesville FL United States Department of Electrical and Computer Engineering University of Texas Austin TX United States Service Computing Technologies and System Lab./Cluster and Grid Computing Lab. HUST Wuhan China Department of Electrical and Computer Engineering Wayne State University MI United States

ISBN: (纸本)9781450319003

Recently, graphics processing units (GPUs) have opened up new opportunities for speeding up general-purpose parallel applications due to their massive computational power and up to hundreds of thousands of threads enabled by programming models such as CUDA. However, due to the serial nature of existing micro-architecture simulators, these massively parallel architectures and workloads need to be simulated sequentially. As a result, simulating GPGPU architectures with typical benchmarks and input data sets is extremely time-consuming. This paper addresses the GPGPU architecture simulation challenge by generating miniature, yet representative GPGPU kernels. We first summarize the static characteristics of an existing GPGPU kernel in a profile, and analyze its dynamic behavior using the novel concept of the divergence flow statistics graph (DFSG). We subsequently use a GPGPU kernel synthesizing framework to generate a miniature proxy of the original kernel, which can reduce simulation time significantly. The key idea is to reduce the number of simulated instructions by decreasing per-thread iteration counts of loops. Our experimental results show that our approach can accelerate GPGPU architecture simulation by a factor of 88X on average and up to 589X with an average IPC relative error of 5.6%.

关键词： Graphics processing unit

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Cross-links matter for link prediction: rethinking the debiased GNN from a data perspective 23

Cross-links matter for link prediction: rethinking the debia...

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Proceedings of the 37th International Conference on Neural Information Processing systems

作者： Zihan Luo Hong Huang Jianxun Lian Xiran Song Xing Xie Hai Jin National Engineering Research Center for Big Data Technology and System Service Computing Technology and Systems Laboratory Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Microsoft Research Asia Beijing China

Recently, the bias-related issues in GNN-based link prediction have raised widely spread concerns. In this paper, we emphasize the bias on links across different node clusters, which we call cross-links, after considering its significance in both easing information cocoons and preserving graph connectivity. Instead of following the objective-oriented mechanism in prior works with compromised utility, we empirically find that existing GNN models face severe data bias between internal-links (links within the same cluster) and cross-links, and this inspires us to rethink the bias issue on cross-links from a data perspective. Specifically, we design a simple yet effective twin-structure framework, which can be easily applied to most GNNs to mitigate the bias as well as boost their utility in an end-to-end manner. The basic idea is to generate debiased node embeddings as demonstrations and fuse them into the embeddings of original GNNs. In particular, we learn debiased node embeddings with the help of augmented supervision signals, and a novel dynamic training strategy is designed to effectively fuse debiased node embeddings with the original node embeddings. Experiments on three datasets with six common GNNs show that our framework can not only alleviate the bias between internal-links and cross-links but also boost the overall accuracy. Comparisons with other state-of-the-art methods also verify the superiority of our method.

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Trust reasoning and optimization based on associate petri net

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ICIC Express Letters 2011年第3期5卷 791-796页

作者： Fang, Xianwen Yan, Chungang Fan, Xiaoqin Yin, Zhixiang Department of Information and Computing Science Anhui University of Science and Technology No. 168 Shungengzhong Road Huainan 232001 China Key Lab of Embedded System and Service Computing Ministry of Education Tongji University No. 1239 Siping Road Shanghai 201804 China

Trust issue is an important problem both in social field and information field. At present, there are few methods considering the interaction behavior relativity between models which can judge the interaction influence, so the obtained trust value is imprecise and unreliable. In the paper, behavior-aware trust computation and reasoning methods based on Associate Petri net (APN) are presented, which use the APN reasoning and take the interaction relativity into account. Using Genetic Algorithm (GA) combined with the properties of APN, a trust optimization method is obtained. Theoretical analysis and experimental results indicate that the method owns both lower computation cost and lower error rate. © 2011 ISSN 1881-803X.

关键词： Genetic algorithms

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GraphInstruct: Empowering Large Language Models with Graph Understanding and Reasoning Capability

arXiv

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arXiv 2024年

作者： Luo, Zihan Song, Xiran Huang, Hong Lian, Jianxun Zhang, Chenhao Jiang, Jinqi Xie, Xing Huazhong University of Science and Technology Wuhan China Microsoft Research Asia Beijing China The National Engineering Research Center for Big Data Technology and System Service Computing Technology and Systems Laboratory Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China

Evaluating and enhancing the general capabilities of large language models (LLMs) has been an important research topic. Graph is a common data structure in the real world, and understanding graph data is a crucial part for advancing general intelligence. To evaluate and enhance the graph understanding abilities of LLMs, in this paper, we propose a benchmark named GraphInstruct, which comprehensively includes 21 classical graph reasoning tasks, providing diverse graph generation pipelines and detailed reasoning steps. Based on GraphInstruct, we further construct GraphLM through efficient instruction-tuning, which shows prominent graph understanding capability. In order to enhance the LLM with graph reasoning capability as well, we propose a step mask training strategy, and construct a model named GraphLM+. As one of the pioneering efforts to enhance the graph understanding and reasoning abilities of LLMs, extensive experiments have demonstrated the superiority of GraphLM and GraphLM+ over other LLMs. We look forward to more researchers exploring the potential of LLMs in the graph data mining domain through GraphInstruct. Our code for generating GraphInstruct is released publicly at: https://***/CGCL-codes/GraphInstruct. Copyright © 2024, The Authors. All rights reserved.

关键词： Computational linguistics

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Hierarchically characterizing CUDA program behavior

Hierarchically characterizing CUDA program behavior

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IEEE International Workshop/Symposium on Workload Characterization

作者： Zhibin Yu Hai Jin Nilanjan Goswami Tao Li Lizy K. John Service Computing Technologies and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Intelligent Design of Efficient Architecture Lab University of Florida Gainesville FL USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

CUDA has become a very popular programming paradigm in parallel computing area. However, very little work has been done for characterizing CUDA kernels. In this work, we measure the thread level performance, collect the basic block level characteristics, and glean the instruction level properties for about 35 programs from CUDA SDK, Parboil, and Rodinia benchmark suites. In addition, we define basic block vectors, synchronization vectors and thread similarity matrix to capture the characteristics of CUDA programs efficiently. We find that CUDA programs have some unique characteristics at each level compared to sequential programs.

关键词： Graphics processing unit Vectors Kernel Instruction sets Programming USA Councils Educational institutions

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