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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Wang, Qinggang Zheng, Long An, Zhaozeng Huang, Haoqin Zhu, Haoran Huang, Yu Yao, Pengcheng Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China

ISBN: (纸本)9798400706011

With the merits of high productivity and ease of use, highlevel synthesis (HLS) tools bring hope to fast FPGA-based architecture development. However, their usability and popularity are still limited due to lack of support for dynamic memory management (DMM). Though HLS-compatible DMM solutions have been proposed recently, nevertheless, based on our investigation, none of them can hit high performance (i.e., minimal memory (de-)allocation latency) and resource efficiency (i.e., managing arbitrarily sized memory with minimal FPGA resource consumption) with one stone, seriously limiting their practicality. In response, we propose HeroDMM, a high-performance and resource-efficient dynamic memory manager for HLS. Specifically, HeroDMM organizes the managed memory area with a novel cartesian-like tree (CT) structure, a key to resolving the dilemma between (de-)allocation latency and resource efficiency standing in front of prior efforts. With the CT structure, HeroDMM further devises a delicate memory management algorithm and specializes the hardware implementation for achieving ever-higher performance while ensuring resource efficiency. Results show that HeroDMM outperforms state-of-the-art HLS-compatible DMM solutions by 61.69%∼99.99% in performance improvement and 23.79%∼97.22% in resource consumption savings. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Memory management

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RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference 24

RTGA: A Redundancy-free Accelerator for High-Performance Tem...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Yu, Hui Zhang, Yu Tan, Andong Lu, Chenze Zhao, Jin Liao, Xiaofei Jin, Hai Liu, Haikun National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China

ISBN: (纸本)9798400706011

Temporal Graph Neural Network (TGNN) has attracted much research attention because it can capture the dynamic nature of complex networks. However, existing solutions suffer from redundant computation overhead and excessive off-chip communications for TGNN inference because they often rely on redundant graph sampling and repeatedly fetching the features and vertex memory. This paper proposes a redundancy-free accelerator, RTGA, for high-performance TGNN inference. Specifically, RTGA proposes a redundancy-aware execution approach with temporal tree into a novel accelerator design to effectively eliminate unnecessary data processing for fewer redundant computations and off-chip communications and also designs a temporal-aware data caching method to improve data locality for TGNN. We have implemented and evaluated RTGA on a Xilinx Alveo U280 FPGA card. Compared with cutting-edge software solutions (i.e., TGN and TGL) and hardware solutions (i.e., BlockGNN and FlowGNN), RTGA improves the performance of TGNN inference by an average of 473.2x, 87.4x, 8.2x, and 6.9x and saves energy by 542.8x, 102.2x, 9.4x, and 8.3x, respectively. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Spatio-temporal data

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Soft-GNN:towards robust graph neural networks via self-adaptive data utilization

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Frontiers of Computer Science 2025年第4期19卷 1-12页

作者： Yao WU Hong HUANG Yu SONG Hai JIN National Engineering Research Center for Big Data Technology and System Service Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China College of Information and Communication National University of Defense TechnologyWuhan 430019China Department of Computer Science and Operations Research Universitéde MontréalMontreal H3C 3J7Canada

Graph neural networks(GNNs)have gained traction and have been applied to various graph-based data analysis tasks due to their high ***,a major concern is their robustness,particularly when faced with graph data that has been deliberately or accidentally polluted with *** presents a challenge in learning robust GNNs under noisy *** address this issue,we propose a novel framework called Soft-GNN,which mitigates the influence of label noise by adapting the data utilized in *** approach employs a dynamic data utilization strategy that estimates adaptive weights based on prediction deviation,local deviation,and global *** better utilizing significant training samples and reducing the impact of label noise through dynamic data selection,GNNs are trained to be more *** evaluate the performance,robustness,generality,and complexity of our model on five real-world datasets,and our experimental results demonstrate the superiority of our approach over existing methods.

关键词： graph neural networks node classification label noise robustness

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Scalable Transactional Stream Processing on Multicore Processors

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IEEE Transactions on Knowledge and Data Engineering 2025年第7期37卷 4254-4269页

作者： Zhao, Jianjun Mao, Yancan Yang, Zhonghao Liu, Haikun Zhang, Shuhao Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China National University of Singapore 119077 Singapore Nanyang Technological University 639798 Singapore

Transactional stream processing engines (TSPEs) are central to modern stream applications handling shared mutable states. However, their full potential, particularly in adaptive scheduling, remains largely unexplored. We present MorphStream, a TSPE designed to optimize parallelism and performance for transactional stream processing on multicores. Through a unique three-stage execution paradigm (i.e., planning, scheduling, and execution), MorphStream enables adaptive scheduling under varying workload characteristics. Building on this foundation, MorphStream is further enhanced with support for non-deterministic state access, employing a stateful task precedence graph to handle undefined read/write sets at runtime while guaranteeing transaction semantics. Additionally, MorphStream incorporates a generalized framework for managing window-based operations, enabling efficient tracking and maintenance of overlapping windows using multi-versioned state management. These extensions enhance the system’s ability to process dynamic and irregular workloads. Experimental results demonstrate up to 3.4 times higher throughput and 69.1% lower latency compared to state-of-the-art TSPEs, validating its scalability and adaptability in real-world streaming scenarios. © 1989-2012 IEEE.

关键词： Multicore programming

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Massively parallel algorithms for fully dynamic all-pairs shortest paths

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Frontiers of Computer Science 2024年第4期18卷 201-203页

作者： Chilei WANG Qiang-Sheng HUA Hai JIN Chaodong ZHENG National Engineering Research Center for Big Data Technology and System Services Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China State Key Laboratory for Novel Software Technology Nanjing UniversityNanjing 210023China

1 Introduction In recent years,the Massively Parallel Computation(MPC)model has gained significant ***,most of distributed and parallel graph algorithms in the MPC model are designed for static graphs[1].In fact,the graphs in the real world are constantly *** size of the real-time changes in these graphs is smaller and more *** graph algorithms[2,3]can deal with graph changes more efficiently[4]than the corresponding static graph ***,most studies on dynamic graph algorithms are limited to the single machine ***,a few parallel dynamic graph algorithms(such as the graph connectivity)in the MPC model[5]have been proposed and shown superiority over their parallel static counterparts.

关键词： dynamic shortest gained

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Media Power Measuring via Emotional Contagion

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Journal of Social computing 2024年第1期5卷 15-35页

作者： Xue Lin Hong Huang Zongya Li Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China School of Journalism Huazhong University of Science and TechnologyWuhan 430074China

Media power,the impact that media have on public opinion and perspectives,plays a significant role in maintaining internal stability,exerting external influence,and shaping international dynamics for nations/***,prior research has primarily concentrated on news content and reporting time,resulting in limitations in evaluating media *** more accurately assess media power,we use news content,news reporting time,and news emotion simultaneously to explore the emotional contagion between *** use emotional contagion to measure the mutual influence between media and regard the media with greater impact as having stronger media *** propose a framework called Measuring Media Power via Emotional Contagion(MMPEC)to capture emotional contagion among media,enabling a more accurate assessment of media power at the media and national/regional *** also interprets experimental results through correlation and causality analyses,ensuring *** analyses confirm the higher accuracy of MMPEC compared to other baseline models,as demonstrated in the context of COVID-19-related news,yielding compelling and interesting insights.

关键词： explainability media power emotional contagion

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TIGA: Towards Efficient Near Data Processing in SmartNICs-based Disaggregated Memory systems 24

TIGA: Towards Efficient Near Data Processing in SmartNICs-ba...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Duan, Zhuohui Yu, Zelin Liu, Haikun Liao, Xiaofei Jin, Hai Zheng, Shijie Wu, Sihan National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9798400706011

Memory disaggregation, facilitated by Smart Network Interface Cards (SmartNICs), has emerged as a cost-effective approach for sharing memory resources in data centers. However, current SoC-based SmartNICs face several challenges for supporting near-data processing (NDP) in disaggregated memory (DM) systems effectively, such as inefficient resource allocation for SmartNICs employed in NDP, and the lack of collaboration between SmartNICs on data nodes and CPUs on compute nodes. To address these issues, we propose TIGA, an efficient NDP framework for SmartNICs-based disaggregated memory systems. We propose an adaptive resource allocator to fully utilize the SoC cores among NDP engines automatically, and a SmartNIC-CPU cooperative computing mechanism to schedule NDP tasks among CPUs and SmartNICs. We prototype TIGA with FPGAs and evaluate it with several typical workloads. Experimental results show that TIGA significantly improves the efficiency of NDP tasks in DM systems compared with state-of-the-art SmartNIC-based co-processing schemes. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Storage allocation (computer)

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Evaluating RISC-V Vector Instruction Set Architecture Extension with Computer Vision Workloads

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Journal of Computer Science & technology 2023年第4期38卷 807-820页

作者：李若时彭平邵志远金海郑然 National Engineering Research Center for Big Data Technology and System Huazhong University of Science and Technology Wuhan 430074China Services Computing Technology and System Laboratory Huazhong University of Science and TechnologyWuhan 430074 China Cluster and Grid Computing Lab Huazhong University of Science and TechnologyWuhan 430074China

Computer vision(CV)algorithms have been extensively used for a myriad of applications *** the multimedia data are generally well-formatted and regular,it is beneficial to leverage the massive parallel processing power of the underlying platform to improve the performances of CV *** Instruction Multiple Data(SIMD)instructions,capable of conducting the same operation on multiple data items in a single instruction,are extensively employed to improve the efficiency of CV *** this paper,we evaluate the power and effectiveness of RISC-V vector extension(RV-V)on typical CV algorithms,such as Gray Scale,Mean Filter,and Edge *** our examinations,we show that compared with the baseline OpenCV implementation using scalar instructions,the equivalent implementations using the RV-V(version 0.8)can reduce the instruction count of the same CV algorithm up to 24x,when processing the same input ***,the actual performances improvement measured by the cycle counts is highly related with the specific implementation of the underlying RV-V *** our evaluation,by using the vector co-processor(with eight execution lanes)of Xuantie C906,vector-version CV algorithms averagely exhibit up to 2.98x performances speedups compared with their scalar counterparts.

关键词： RISC-V vector extension single instruction multiple data(SIMD) computer vision OpenCV

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Towards High-throughput and Low-latency Billion-scale Vector Search via CPU/GPU Collaborative Filtering and Re-ranking 23

Towards High-throughput and Low-latency Billion-scale Vector...

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23rd USENIX Conference on File and Storage Technologies, FAST 2025

作者： Tian, Bing Liu, Haikun Tang, Yuhang Xiao, Shihai Duan, Zhuohui Liao, Xiaofei Jin, Hai Zhang, Xuecang Zhu, Junhua Zhang, Yu National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Huawei Technologies Co. Ltd. China

ISBN: (纸本)9781939133458

Approximate nearest neighbor search (ANNS) has emerged as a crucial component of database and AI infrastructure. Ever-increasing vector datasets pose significant challenges in terms of performance, cost, and accuracy for ANNS services. None of modern ANNS systems can address these issues simultaneously. In this paper, we present FusionANNS, a high-throughput, low-latency, cost-efficient, and high-accuracy ANNS system for billion-scale datasets using SSDs and only one entry-level GPU. The key idea of FusionANNS lies in CPU/GPU collaborative filtering and re-ranking mechanisms, which significantly reduce I/O operations across CPUs, GPU, and SSDs to break through the I/O performance bottleneck. Specifically, we propose three novel designs: (1) multi-tiered indexing to avoid data swapping between CPUs and GPU, (2) heuristic re-ranking to eliminate unnecessary I/Os and computations while guaranteeing high accuracy, and (3) redundant-aware I/O deduplication to further improve I/O efficiency. We implement FusionANNS and compare it with the state-of-the-art SSD-based ANNS system-SPANN and GPU-accelerated in-memory ANNS system-RUMMY. Experimental results show that FusionANNS achieves 1) 9.4-13.1× higher query per second (QPS) and 5.7-8.8× higher cost efficiency compared with SPANN;2) and 2-4.9× higher QPS and 2.3-6.8× higher cost efficiency compared with RUMMY, while guaranteeing low latency and high accuracy. © 2025 FAST. All Rights Reserved.

关键词： Collaborative filtering

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SpaHet: A Software/Hardware Co-design for Accelerating Heterogeneous-Sparsity based Sparse Matrix Multiplication 24

SpaHet: A Software/Hardware Co-design for Accelerating Heter...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Huang, Haoqin Yao, Pengcheng An, Zhaozeng Sun, Yufei Hu, Ao Xu, Peng Zheng, Long Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan430074 China Zhejiang Lab Hangzhou311121 China

ISBN: (纸本)9798400706011

Sparse general matrix-matrix multiplication is widely used in data mining applications. Its irregular memory access patterns limit the performance of general-purpose processors, thus motivating many FPGA-based hardware innovations in recent years. Nevertheless, existing accelerators fail to efficiently support heterogeneous input matrix sparsity, which is universal in various real-world applications. With in-depth experimental analysis, we observe that their performance is bottlenecked by their fixed tiling mechanisms, which only alleviate the irregularity of one input matrix. Based on the observation, we propose SpaHet, a software/hardware co-design to accelerate heterogeneous-sparsity based sparse matrix multiplication. SpaHet adopts a dual-adaptive sliding window mechanism to cover the reuse characteristics of both input matrices simultaneously. With a specialized exploration algorithm, the window-based mechanism can automatically find the optimal tiling strategy instead of applying a fixed one based on empirical experience. A sparsity-aware merge tree is also proposed to maximize the output matrix reuse via accumulating intermediate results thoroughly. Our results on a Xilinx Alveo U280 accelerator card show that SpaHet outperforms state-of-the-art CPU-, GPU- and FPGA-based solutions by 7.71×, 1.1×, and 2.74× in performance, respectively. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Program processors

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