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International Conference on Software Engineering (ICSE)

作者： Maolin Sun Yibiao Yang Ming Wen Yongcong Wang Yuming Zhou Hai Jin School of Cyber Science and Engineering Huazhong University of Science and Technology China Hubei Key Laboratory of Distributed System Security Services Computing Technology and System Lab Cluster and Grid Computing Lab Hubei Engineering Research Center on Big Data Security National Engineering Research Center for Big Data Technology and System State Key Laboratory for Novel Software Technology Nanjing University China School of Computer Science and Technology Huazhong University of Science and Technology China

SMT solvers check the satisfiability of logic formulas over first-order theories, which have been utilized in a rich number of critical applications, such as software verification, test case generation, and program synthesis. Bugs hidden in SMT solvers would severely mislead those applications and further cause severe consequences. Therefore, ensuring the reliability and robustness of SMT solvers is of critical importance. Although many approaches have been proposed to test SMT solvers, it is still a challenge to discover bugs effectively. To tackle such a challenge, we conduct an empirical study on the historical bug-triggering formulas in SMT solvers' bug tracking systems. We observe that the historical bug-triggering formulas contain valuable skeletons (i.e., core structures of formulas) as well as associated atomic formulas which can cast significant impacts on formulas' ability in triggering bugs. Therefore, we propose a novel approach that utilizes the skeletons extracted from the historical bug-triggering formulas and enumerates atomic formulas under the guidance of association rules derived from historical formulas. In this study, we realized our approach as a practical fuzzing tool HistFuzz and conducted extensive testing on the well-known SMT solvers Z3 and cvc5. To date, HistFuzz has found 111 confirmed new bugs for Z3 and cvc5, of which 108 have been fixed by the developers. More notably, out of the confirmed bugs, 23 are soundness bugs and invalid model bugs found in the solvers' default mode, which are essential for SMT solvers. In addition, our experiments also demonstrate that HistFuzz outperforms the state-of-the-art SMT solver fuzzers in terms of achieved code coverage and effectiveness.

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Heterogeneous differential privacy for vertically partitioned databases

Heterogeneous differential privacy for vertically partitione...

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作者： Xia, Yang Zhu, Tianqing Ding, Xiaofeng Jin, Hai Zou, Deqing National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Deakin University Victoria Australia

Existing privacy-preserving approaches are generally designed to provide privacy guarantee for individual data in a database, which reduces the utility of the database for data analysis. In this paper, we propose a novel differential privacy mechanism to preserve the heterogeneous privacy of a vertically partitioned database based on attributes. We first present the concept of privacy label, which characterizes the privacy information of the database and is instantiated by the classification. Then, we use an information-based method to systematically explore the dependencies between all attributes and the privacy label. We finally assign privacy weights to every attribute and design a heterogeneous mechanism according to the basic Laplace mechanism. Evaluations using real datasets demonstrate that the proposed mechanism achieves a balanced privacy and utility. © 2019 John Wiley & Sons, Ltd.

关键词： database systems

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Fast and Scalable Gate-Level Simulation in Massively Parallel systems

Fast and Scalable Gate-Level Simulation in Massively Paralle...

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IEEE International Conference on Computer-Aided Design

作者： Haichuan Hu Zichen Xu Yuhao Wang Fangming Liu Services Computing Technology and System Lab Cluster and Grid Computing Lab National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Mathematics and Computer Science Nanchang University Nanchang China Pengcheng Laboratory Shenzhen China

The natural bijection between a proposed circuit design and its graph representation shall allow any graph optimization algorithm deploying into many-core systems efficiently. However, this process suffers from the exponentially growing overhead and heavy memory footprint with the signal propagation. To conquer the unique challenge, we systematically study the simulation with millions of gates, and identify that the processing complexity could grow exponentially from the signal inputs, the skewness of the computational graph stays. Thus, we present ZhouBi, a fast and scalable gate-level simulation framework to fully exploit the parallelism from many-core systems. ZhouBi contributes in threefolds, (I) a graph representation that colors gate-level netlists and identifies skew partitions based on the graph skewness; (II) A set of heuristic algorithms that picks opportunistic and conservative algorithms to accelerate the simulation; (III) A system facility that supports selective mapping between simulation and many-core, providing a tradeoff between the risk of concurrent simulation fail and performance gain. We have prototyped ZhouBi and evaluated it with practical baselines. ZhouBi can achieve a 27.6× performance gain, as compared to the state-of-the-practice Veriwell without compromising any correctness. Our framework supports large graphs enabling scale-out gate-level simulations for chip design.

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Iterative Refinement of Project-Level Code Context for Precise Code Generation with Compiler Feedback

arXiv

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arXiv 2024年

作者： Bi, Zhangqian Wan, Yao Wang, Zheng Zhang, Hongyu Guan, Batu Lu, Fangxin Zhang, Zili Sui, Yulei Jin, Hai Shi, Xuanhua Huazhong University of Science and Technology China University of Leeds United Kingdom Chongqing University China Shanghai Jiao Tong University China University of New South Wales Australia National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

Large Language Models (LLMs) have shown remarkable progress in automated code generation. Yet, LLM-generated code may contain errors in API usage, class, data structure, or missing project-specific information. As much of this project-specific context cannot fit into the prompts of LLMs, we must find ways to allow the model to explore the project-level code context. We present COCOGEN, a new code generation approach that uses compiler feedback to improve the LLM-generated code. COCOGEN first leverages static analysis to identify mismatches between the generated code and the project’s context. It then iteratively aligns and fixes the identified errors using information extracted from the code repository. We integrate COCOGEN with two representative LLMs, i.e., GPT-3.5-Turbo and Code Llama (13B), and apply it to Python code generation. Experimental results show that COCOGEN significantly improves the vanilla LLMs by over 80% in generating code dependent on the project context and consistently outperforms the existing retrieval-based code generation baselines. © 2024, CC BY-NC-SA.

关键词： Static analysis

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Design and Simulation of Multi-tiered Heterogeneous Memory Architecture

Design and Simulation of Multi-tiered Heterogeneous Memory A...

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International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems (MASCOTS)

作者： Jinyuan Hu Haikun Liu Hai Jin Xiaofei Liao National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Heterogeneous memory systems have become increasingly popular in recent years. Because heterogeneous storage media often show significantly different characteristics in terms of bandwidth, latency, capacity, and energy consumption, it is still challenging to best utilize them for cost-efficient and energy-efficient heterogeneous memory systems. In this paper, we propose a simulation framework for multi-tiered heterogeneous memory architectures based on GEM5 and DRAMsim3 simulators. We design a heterogeneous memory controller to architect Non-Volatile Memory (NVM) as main memory, and architect both Dynamic Random Access Memory (DRAM) and High-Bandwidth Memory (HBM) as a hybrid cache of NVM. Specifically, HBM, DRAM, and NVM are managed in a single (flat) address space. However, we use an address remapping table to maintain the mappings between NVM pages and HBM/DRAM pages, and logically manage HBM/DRAM/NVM as a three-tiered hybrid memory system. We also design a hardware-supported hot page monitor based on Majority Element Algorithm (MEA) to identify the hottest pages in the DRAM, and a dynamic threshold adjustment scheme for hot page migration to balance the memory bandwidth between DRAM and HBM. Our multi-tiered heterogeneous memory architecture can take advantage of the large capacity of NVM, the low latency of DRAM, and the high bandwidth of HBM concurrently. Experimental results show that our tiered memory architecture can improve application performance by an average of $2.5\times$ compared with an NVM-only architecture, and up to 57.4% compared with a DRAM-only architecture. Moreover, the performance gap between our HBM/DRAM/NVM architecture and a HBM-only architecture is less than 10%.

关键词： Analytical models Nonvolatile memory Heuristic algorithms Computational modeling Memory architecture Random access memory Computer architecture

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CPSAA: Accelerating Sparse Attention using Crossbar-based Processing-In-Memory Architecture

arXiv

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arXiv 2022年

作者： Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei Huang, Yu Liu, Cong Xu, Jiahong Duan, Zhuohui Chen, Dan Gui, Chuangyi National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The attention-based neural network attracts great interest due to its excellent accuracy enhancement. However, the attention mechanism requires huge computational efforts to process unnecessary calculations, significantly limiting the system’s performance. To reduce the unnecessary calculations, researchers propose sparse attention to convert some dense-dense matrices multiplication (DDMM) operations to sampled dense-dense matrix multiplication (SDDMM) and sparse matrix multiplication (SpMM) operations. However, current sparse attention solutions introduce massive off-chip random memory access since the sparse attention matrix is generally unstructured. We propose CPSAA, a novel crossbar-based processing-in-memory (PIM)-featured sparse attention accelerator to eliminate off-chip data transmissions. First, we present a novel attention calculation mode to balance the crossbar writing and crossbar processing latency. Second, we design a novel PIM-based sparsity pruning architecture to eliminate the pruning phase’s off-chip data transfers. Finally, we present novel crossbar-based SDDMM and SpMM methods to process unstructured sparse attention matrices by coupling two types of crossbar arrays. Experimental results show that CPSAA has an average of 89.6×, 32.2×, 17.8×, 3.39×, and 3.84× performance improvement and 755.6×, 55.3×, 21.3×, 5.7×, and 4.9× energy-saving when compare with GPU, FPGA, SANGER, ReBERT, and ReTransformer. Copyright © 2022, The Authors. All rights reserved.

关键词： Memory architecture

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Variational Bayes for Federated Continual Learning

arXiv

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arXiv 2024年

作者： Yao, Dezhong Li, Sanmu Dai, Yutong Xu, Zhiqiang Hu, Shengshan Zhao, Peilin Sun, Lichao The National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab. Cluster and Grid Computing Lab. School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Lehigh University PA18015 United States Mohamed bin Zayed University of Artificial Intelligence United Arab Emirates Tencent AI Lab. Shenzhen China

Federated continual learning (FCL) has received increasing attention due to its potential in handling real-world streaming data, characterized by evolving data distributions and varying client classes over time. The constraints of storage limitations and privacy concerns confine local models to exclusively access the present data within each learning cycle. Consequently, this restriction induces performance degradation in model training on previous data, termed "catastrophic forgetting". However, existing FCL approaches need to identify or know changes in data distribution, which is difficult in the real world. To release these limitations, this paper directs attention to a broader continuous framework. Within this framework, we introduce Federated Bayesian Neural Network (FedBNN), a versatile and efficacious framework employing a variational Bayesian neural network across all clients. Our method continually integrates knowledge from local and historical data distributions into a single model, adeptly learning from new data distributions while retaining performance on historical distributions. We rigorously evaluate FedBNN’s performance against prevalent methods in federated learning and continual learning using various metrics. Experimental analyses across diverse datasets demonstrate that FedBNN achieves state-of-the-art results in mitigating forgetting. Copyright © 2024, The Authors. All rights reserved.

关键词： Digital storage

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Diabetes Mellitus Type 2 data Sharing system Based on Blockchain and Attribute-Encryption

Diabetes Mellitus Type 2 Data Sharing System Based on Blockc...

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IEEE International Conference on Trust, Security and Privacy in computing and Communications (TrustCom)

作者： Weiqi Dai Zhenhui Lu Xia Xie Duoqiang Wang Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Hubei Engineering Research Center on Big Data Security School of Cyber Science and Engineering Huazhong University of Science and Technology Wuhan China National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computer Science and Technology Hainan University Haikou China

Medical data sharing can improve the quality of medical care and promote progress in the field of public health. However, medical data has high confidentiality and complexity. Taking the clinical diagnosis and treatment data of Diabetes Mellitus Type 2 (T2DM) in medical treatment as an example, T2DM data often has the phenomenon of "multi-disease coexistence" and is insecure and inaccurate in the process of sharing. Based on Blockchain and Attribute- Encryption (ABE), we propose a T2DM data sharing system to solve the above problems. An Attribute-Encryption algorithm T2DM-CP-ABE is proposed to solve the problem of excessive sharing granularity. T2DM-CP-ABE, combined with the medical data contribution module, takes the contribution factor as an important consideration, to stimulate the power of T2DM data sharing and promote the development of national diabetes prevention. Based on the Blockchain, a medical data attribute authorization model is proposed, which provides a credible solution for multiple hospitals to realize medical data attribute authorization, and realizes the clinical diagnosis and treatment data sharing of T2DM among doctors. Based on Blockchain and ABE technology, a data sharing system for T2DM has been implemented on the Fabric platform. The result shows that the average time for the system to complete a single sharing is less than 1 second.

关键词： Authorization Hospitals Fabrics Blockchains Diabetes Encryption Security

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Shared Incentive system for Clinical Pathway Experience

Shared Incentive System for Clinical Pathway Experience

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IEEE International Conference on Trust, Security and Privacy in computing and Communications (TrustCom)

作者： Weiqi Dai Wenhao Zhao Xia Xie Song Wu Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Hubei Engineering Research Center on Big Data Security School of Cyber Science and Engineering Huazhong University of Science and Technology Wuhan China National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computer Science and Technology Hainan University Haikou China

The phenomenon of unbalanced regional medical resources has led to large differences in the implementation experience of clinical pathways in hospitals with different medical levels. However, due to the fear of privacy leakage and the lack of sharing motivation, there is a lack of effective collaborative communication channels for clinical pathways among medical institutions. In response to these problems, we propose a blockchain-based sharing incentive scheme for clinical pathway experience, which uses the clinical pathway implementation effect evaluation system to evaluate the quality of clinical pathway experience data. Specifically, we designe a two-phase cross-domain shared transaction model for the transaction of clinical pathway experience data. Moreover, we introduce the shared transaction alliance committee to verify and review the transaction, and solve the problems in the transaction in the arbitration phase. Finally, the functional test results show that the system meets the experience sharing incentive requirements, and the performance test results show that the TPS of sharing clinical pathway experience read and writed can reach around 600 and 1000, and the transaction latency of each phase is within 3 s.

关键词： Privacy Hospitals Collaboration Communication channels data models Security Incentive schemes

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Reconciling Selective Logging and Hardware Persistent Memory Transaction

Reconciling Selective Logging and Hardware Persistent Memory...

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IEEE Symposium on High-Performance Computer Architecture

作者： Chencheng Ye Yuanchao Xu Xipeng Shen Yan Sha Xiaofei Liao Hai Jin Yan Solihin National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China North Carolina State University Raleigh North Carolina USA University of Central Florida Florida USA

Log creation, maintenance, and its persist ordering are known to be performance bottlenecks for durable transactions on persistent memory. Existing hardware persistent memory transactions overlook an important opportunity for improving performance: some persistent data is algorithmically redundant such that it can be recovered from other data, removing the need for logging such data. The paper presents an ISA extension that enables selective logging for hardware persistent memory transactions for the first time. The ISA extension features two novel components: fine-grain logging and lazy persistency. Fine-grain logging allows hardware to log updates on data in the granularity of words without lengthening the critical path of data accesses. Lazy persistency allows updated data to remain in the cache after the transaction commits. Together, the new hardware persistent memory transaction outperforms the state-of-the-art hardware counterpart by 1.8× on average.

关键词： Computer architecture Maintenance engineering Hardware Optimization IEEE transactions

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