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作者： Xu, Hui Ding, Xiaofeng Jin, Hai Yu, Qing National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Although cloud computing saves the cost of enterprises and individuals to manage data in various applications on public cloud servers, it also causes the problem of the leakage of critical personal information and sensitive data. Therefore, the issues about data privacy of the published personal information have become a challenging problem. Most of the existing methods focus on cryptography-based techniques by encrypting the sensitive data before publishing. However, these techniques are either too computation expensive or only some authorized users can get access to the encrypted cloud data. The consequence is that the search response time is not satisfactory and the sharing extent of the cloud data is becoming limited. Motivated by this, we propose a perturbation-based method to preserve the privacy of data in cloud. To accelerate the query processing without privacy breaches, a high-efficiency multi-dimensional index is built for answering range counting queries under differential privacy, which embeds privacy-preserving R-tree index in Content Addressable Network. Experimental results demonstrate that our methods not only protect data privacy in different degree, but also accelerate the query speed efficiently. Compared with the existing method Quad-opt, our method provides about 20% better data utility under the same differential privacy principles. © 2019 John Wiley & Sons, Ltd.

关键词： Sensitive data

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RGraph: Asynchronous graph processing based on asymmetry of remote direct memory access

RGraph: Asynchronous graph processing based on asymmetry of ...

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作者： Chen, Hanhua Yuan, Jie Jin, Hai Wang, Yonghui Wu, Sijie Jiang, Zhihao National Engineering Research Center for Big Data Technology and System Cluster and Grid Computing Lab Services Computing Technology and System Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The scale of real-world graphs is constantly growing. To deal with large-scale graphs, distributed graph processing has attracted much research efforts. Existing distributed graph processing systems are commonly built on traditional TCP/IP communication stack, which leads to network bottleneck because of low bandwidth and heavy kernel stack operations. Meanwhile, in real power-law graphs, the average number of mirror vertices after graph partitioning is very large, resulting in significant communication overhead among nodes. The emerging high-performance Remote Direct Memory Access (RDMA) network has the features of low latency, high bandwidth, and low CPU overhead, which brings new opportunities for distributed graph processing systems. Existing RDMA-assisted graph processing systems focus on synchronous execution, which imposes barriers between consecutive iterations. Synchronous execution transfers bulk data among nodes and thus only needs a small number of network transfers. However, synchronous execution is usually less efficient than asynchronous execution because of bulk synchronization. Asynchronous execution accelerates graph processing by eliminating barriers, which in turn requires to transfer a large amount of small size data. In this paper, we propose RGraph, an RDMA-assisted asynchronous distributed graph processing system. RGraph distributes edges into two parts to isolate master and mirror vertices. RGraph exploits the asymmetry of RDMA to accelerate the one-to-many communication between master and mirror vertices. We implement RGraph on top of PowerGraph and conduct comprehensive experiments with large-scale real graphs to evaluate its performance. Results show that compared to existing designs, RGraph reduces the execution time by up to 81%. © 2021 John Wiley & Sons Ltd.

关键词： Mirrors

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Fine-grained Scheduling in FPGA-Based Convolutional Neural Networks 5

Fine-grained Scheduling in FPGA-Based Convolutional Neural N...

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5th IEEE International Conference on Cloud computing and Big Data Analytics, ICCCBDA 2020

作者： Zhang, Wei Liao, Xiaofei Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan China

ISBN: (纸本)9781728160245

FPGA has been considered as a promising solution to accelerate Convolutional Neural Networks (CNNs) for its excellent performance in energy efficiency and programmability. However, prior designs are usually designed for inference only as designers can map pre-trained models to the hardware in a very efficient way. However, those approaches may not be suitable for training CNN models. In this paper, we propose FConv, in which the CPU and FPGA work together in a fine-grained manner. The FPGA accelerator in FConv uses one Winograd-based convolver, which reduces the design complexity and improves performance. We apply double-buffer for output routine to effectively overlap computation and data transfer. We also integrate multiple PEs to improve data parallelism. We propose our analytical model for prediction and use it as a guide in task scheduling. We find the upper limit of performance under the current design based on the analytical model. We evaluate our design on VGG-16 and Densnet-40 on ImageNet and CIFAR-10. We achieve 262.43 GOP/s on the VGG-16 model, which is 2.13 times of the performance compared to FFT-based implementation on the same platform. We also achieve at most 4 times+ performance improvement compared MKL with 20 threads running on 10 core Intel processors. © 2020 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A Survey of Non-Volatile Main Memory Technologies:State-of-the-Arts,Practices,and Future Directions

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Journal of Computer Science & technology 2021年第1期36卷 4-32页

作者： Hai-Kun Liu Di Chen Hai Jin Xiao-Fei Liao Binsheng He Kan Hu Yu Zhang National Engineering Research Center for Big Data Technology and System Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory Huazhong University of Science and Technology Wuhan 430074China Cluster and Grid Computing Laboratory Huazhong University of Science and TechnologyWuhan 430074China School of Computing Science and Technology Huazhong University of Science and TechnologyWuhan 430074China School of Computing National University of SingaporeSingapore 117418Singapore

Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.

关键词： non-volatile memory persistent memory hybrid memory systems memory hierarchy

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SpaHet: A Software/Hardware Co-design for Accelerating Heterogeneous-Sparsity based Sparse Matrix Multiplication 24

SpaHet: A Software/Hardware Co-design for Accelerating Heter...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Huang, Haoqin Yao, Pengcheng An, Zhaozeng Sun, Yufei Hu, Ao Xu, Peng Zheng, Long Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan430074 China Zhejiang Lab Hangzhou311121 China

ISBN: (纸本)9798400706011

Sparse general matrix-matrix multiplication is widely used in data mining applications. Its irregular memory access patterns limit the performance of general-purpose processors, thus motivating many FPGA-based hardware innovations in recent years. Nevertheless, existing accelerators fail to efficiently support heterogeneous input matrix sparsity, which is universal in various real-world applications. With in-depth experimental analysis, we observe that their performance is bottlenecked by their fixed tiling mechanisms, which only alleviate the irregularity of one input matrix. Based on the observation, we propose SpaHet, a software/hardware co-design to accelerate heterogeneous-sparsity based sparse matrix multiplication. SpaHet adopts a dual-adaptive sliding window mechanism to cover the reuse characteristics of both input matrices simultaneously. With a specialized exploration algorithm, the window-based mechanism can automatically find the optimal tiling strategy instead of applying a fixed one based on empirical experience. A sparsity-aware merge tree is also proposed to maximize the output matrix reuse via accumulating intermediate results thoroughly. Our results on a Xilinx Alveo U280 accelerator card show that SpaHet outperforms state-of-the-art CPU-, GPU- and FPGA-based solutions by 7.71×, 1.1×, and 2.74× in performance, respectively. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Program processors

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GraSU: A fast graph update library for fpga-based dynamic graph processing 21

GraSU: A fast graph update library for fpga-based dynamic gr...

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2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2021

作者： Wang, Qinggang Zheng, Long Huang, Yu Yao, Pengcheng Gui, Chuangyi Liao, Xiaofei Jin, Hai Jiang, Wenbin Mao, Fubing National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology China

ISBN: (纸本)9781450382182

Existing FPGA-based graph accelerators, typically designed for static graphs, rarely handle dynamic graphs that often involve substantial graph updates (e.g., edge/node insertion and deletion) over time. In this paper, we aim to fill this gap. The key innovation of this work is to build an FPGA-based dynamic graph accelerator easily from any off-the-shelf static graph accelerator with minimal hardware engineering efforts (rather than from scratch). We observe\em spatial similarity of dynamic graph updates in the sense that most of graph updates get involved with only a small fraction of vertices. We therefore propose an FPGA library, called GraSU, to exploit spatial similarity for fast graph updates. GraSU uses a differential data management, which retains the high-value data (that will be frequently accessed) in the specialized on-chip UltraRAM while the overwhelming majority of low-value ones reside in the off-chip memory. Thus, GraSU can transform most of off-chip communications arising in dynamic graph updates into fast on-chip memory accesses. Our experiences show that GraSU can be easily integrated into existing state-of-the-art static graph accelerators with only 11 lines of code modifications. Our implementation atop AccuGraph using a Xilinx Alveo#8482;\U250 board outperforms two state-of-the-art CPU-based dynamic graph systems, Stinger and Aspen, by an average of 34.24× and 4.42× in terms of update throughput, improving further overall efficiency by 9.80× and 3.07× on average. © 2021 ACM.

关键词： Field programmable gate arrays (FPGA)

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High Performance DDoS Attack Detection system Based on Distribution Statistics 16th

High Performance DDoS Attack Detection System Based on Distr...

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16th IFIP WG 10.3 International Conference on Network and Parallel computing, NPC 2019

作者： Xie, Xia Li, Jinpeng Hu, Xiaoyang Jin, Hai Chen, Hanhua Ma, Xiaojing Huang, Hong National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783030307080

Nowadays, web servers often face the threat of distributed denial of service attacks and their intrusion prevention systems cannot detect those attacks effectively. Many existing intrusion prevention systems detect attacks by the state of per-flow and current processing speed cannot fulfill the requirements of real-time detection due to the high speed traffic. In this paper, we propose a powerful system TreeSketchShield which can improve sketch data structure and detect attacks quickly. First, we discuss a novel structure TreeSketch to obtain statistics of network flow, which utilizes the stepped structure of binary tree to map the distribution and reduces the complexity of the statistic calculation. Second, we present a two-level detection scheme that could make a compromise between the detection speed and detection accuracy. Experimental results show that our method can process more than 100,000 records per second. The false alarm rate can achieve 2% to 25% performance improvement. © 2019, IFIP International Federation for Information Processing.

关键词： Binary trees

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An Efficient Data Prefetch Strategy for Deep Learning Based on Non-volatile Memory 15th

An Efficient Data Prefetch Strategy for Deep Learning Based ...

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15th International Conference on Green, Pervasive, and Cloud computing, GPC 2020

作者： Jiang, Wenbin Liu, Pai Jin, Hai Peng, Jing National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783030642426

Deep learning (DL) systems usually utilize asynchronous prefetch to improve data reading performance. However, the efficiency of the data transfer path from hard disk to DRAM is still limited by disk performance. The emerging non-volatile memory (NVRAM) provides a novel solution for this problem, while few existing researches have considered it. We propose a novel efficient data prefetch strategy for DL based on a heterogeneous memory system combining NVRAM with DRAM. Benefitting from the large capacity and fast reading speed of NVRAM, the strategy uses an asynchronous reading method named sliding NVRAM cache (SNC) to improve the performance of the data transfer paths. A sliding window is applied to map the data from disk to NVRAM and continuously update the data, while non-ideal writing performance of NVRAM can be remitted to a large extent in this strategy. Experiments show that SNC can improve the time performance of diverse deep neural networks training by more than 30%. © 2020, Springer Nature Switzerland AG.

关键词： Dynamic random access storage

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Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory Processing 24

Towards Redundancy-Free Recommendation Model Training via Re...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Liu, Haifeng Zheng, Long Huang, Yu Huang, Haoyan Liao, Xiaofei Hai, Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan430074 China Zhejiang Lab Hangzhou311121 China

ISBN: (纸本)9798400706011

The memory-intensive embedding layer in recommendation model continues to be the performance bottleneck. While prior works have attempted to improve the embedding layer performance by exploiting the data locality to cache the frequently accessed embedding vectors and their partial sums. However, these solutions rely on the static cache, which is inapplicable in the embedding training scenario where the embedding vectors are updated frequently. To this end, this paper proposes ReFree, a redundancy-free near-memory processing (NMP) solution for recommendation model training. Specifically, ReFree identifies the reusable data in realtime for both embedding layer forward and backward stages and leverages a lightweight NMP architecture to enable redundancy-free near-memory acceleration of the entire embedding training process. Evaluation results on real-world datasets show that ReFree outperforms the state-of-the-art solutions by 10.9× and reduces 5.3× energy consumption on average. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Embeddings

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Anole: A Lightweight and Verifiable Learned-Based Index for Time Range Query on Blockchain systems 28th

Anole: A Lightweight and Verifiable Learned-Based Index for...

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28th International Conference on Database systems for Advanced Applications, DASFAA 2023

作者： Chang, Jian Li, Binhong Xiao, Jiang Lin, Licheng Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783031306365

Time range query is essential to facilitate a wide range of blockchain applications such as data provenance in the supply chain. Existing blockchain systems adopt the storage-consuming tree-based index structure for better query performance, however, fail to efficiently work for most blockchain nodes with limited resources. In this paper, we propose Anole, a lightweight and verifiable time range query mechanism, to present the feasibility of building up a learned-based index to achieve high performance and low storage costs on blockchain systems. The key idea of Anole is to exploit the temporal characteristics of blockchain data distribution and design a tailored lightweight index to reduce storage costs. Moreover, it uses a digital signature to guarantee the correctness and completeness of query results by considering the learned index’s error bounds, and applies batch verification to further improve verification performance. Experimental results demonstrate that Anole improves the query performance by up to 10 × and reduces the storage overhead by 99.4 % compared with the state-of-the-art vChain+. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Blockchain

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