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36th International Conference on Massive Storage systems and technology, MSST 2020

作者： Liu, Haikun Ye, Yuanyuan Liao, Xiaofei Jin, Hai Zhang, Yu Jiang, Wenbin He, Bingsheng National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China School of Computing National University of Singapore Singapore

Emerging Non-Volatile Main Memory (NVMM) technologies generally feature high density, low energy consumption and cost per bit compared to DRAM. However, the limited write endurance of NVMM poses a significant challenge of using NVMM as an substitute for DRAM. This paper proposes a space-oblivious compression and wear-leveling based memory architecture to improve the write endurance of NVMM. As memory blocks of many applications usually contain a large amount of zero bytes and frequent values, we propose a nonuniform compression encoding scheme that integrates Zero Deduplication with Frequent Value Compression (called ZD-FVC) to reduce bit-writes on NVMM. Moreover, we leverage the memory space available through compression to achieve an intra-block wear leveling policy. It rotates the writing positions of a compressed data block within the data’s initial memory space, and thus enhances write endurance by balancing the bit-writes per NVMM cell. ZD-FVC can be integrated into the NVMM module and implemented entirely by hardware, without any intervention of Operating systems. We implement ZD-FVC in Gem5 and NVMain simulators, and evaluate it with several programs from SPEC CPU2006. Experimental results shows that ZD-FVC is much better than several state-of-the-art approaches. Particularly, ZD-FVC can improve data compression ratio by 55% compared to Frequent Value Compression. Compared with the Data Comparison Write, ZD-FVC is able to significantly improve the lifetime of NVMM by 3.3X on average, and also reduces NVMM write latency by 31% and energy consumption by 19% on average. © 2020 36th International Conference on Massive Storage systems and technology, MSST 2020. All Rights Reserved.

关键词： Dynamic random access storage

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A Survey on Graph Processing Accelerators:Challenges and Opportunities

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Journal of Computer Science & technology 2019年第2期34卷 339-371页

作者： Chuang-Yi Gui Long Zheng Bingsheng He Cheng Liu Xin-Yu Chen Xiao-Fei Liao Hai Jin National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China Cluster and Grid Computing Laboratory School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China School of Computing National University of Singapore Singapore 117418 Singapore Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Graph is a well known data structure to represent the associated relationships in a variety of applications,e.g.,data science and machine *** a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures,dedicated hardware solutions,also referred to as graph processing accelerators,are essential and emerging to provide the benefits significantly beyond what those pure software solutions can *** this paper,we conduct a systematical survey regarding the design and implementation of graph processing ***,we review the relevant techniques in three core components toward a graph processing accelerator:preprocessing,parallel graph computation,and runtime *** also examine the benchmarks and results in existing studies for evaluating a graph processing ***,we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and the complexity of hardware *** finally present and discuss several challenges in details,and further explore the opportunities for the future research.

关键词： graph processing accelerator domain-specific architecture performance energy efficiency

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An Efficient Graph Accelerator with Distributed On-Chip Memory Hierarchy 22nd

An Efficient Graph Accelerator with Distributed On-Chip Mem...

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22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022

作者： Zheng, Ran Jiang, Yingxin Wang, Yibo Su, Yongbo Zheng, Long Yao, Pengcheng Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Zhejiang Lab Hangzhou311121 China

ISBN: (纸本)9783031226762

Graph processing has evolved and expanded swiftly with artificial intelligence and big data technology. High-Bandwidth Memory (HBM), which delivers terabyte-level memory bandwidth, has opened up new development possibilities for FPGA-based graph accelerators. However, despite the tremendous expansion of underlying hardware capabilities, existing graph accelerators have not benefited too much. In this paper, we observe that the uniformed on-chip memory hierarchy is the key to the low scalability of existing graph accelerators. We present a novel graph accelerator with a distributed on-chip memory hierarchy called GraphS. The on-chip memory of GraphS is divided into numerous tiny blocks, each of which is assigned to only one Processing Element (PE). Different PEs are connected through a scalable network-on-chip (NoC). For realistic graphs with power-law properties, a degree-aware preprocessing method is designed to balance the workload among different PEs. Our results with various graph algorithms demonstrate that GraphS can outperform state-of-the-art ForeGraph by up to 21.84 ×. © 2023, Springer Nature Switzerland AG.

关键词： Network-on-chip

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High-Performance and Resource-Efficient Dynamic Memory Management in High-Level Synthesis 24

High-Performance and Resource-Efficient Dynamic Memory Manag...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Wang, Qinggang Zheng, Long An, Zhaozeng Huang, Haoqin Zhu, Haoran Huang, Yu Yao, Pengcheng Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China

ISBN: (纸本)9798400706011

With the merits of high productivity and ease of use, highlevel synthesis (HLS) tools bring hope to fast FPGA-based architecture development. However, their usability and popularity are still limited due to lack of support for dynamic memory management (DMM). Though HLS-compatible DMM solutions have been proposed recently, nevertheless, based on our investigation, none of them can hit high performance (i.e., minimal memory (de-)allocation latency) and resource efficiency (i.e., managing arbitrarily sized memory with minimal FPGA resource consumption) with one stone, seriously limiting their practicality. In response, we propose HeroDMM, a high-performance and resource-efficient dynamic memory manager for HLS. Specifically, HeroDMM organizes the managed memory area with a novel cartesian-like tree (CT) structure, a key to resolving the dilemma between (de-)allocation latency and resource efficiency standing in front of prior efforts. With the CT structure, HeroDMM further devises a delicate memory management algorithm and specializes the hardware implementation for achieving ever-higher performance while ensuring resource efficiency. Results show that HeroDMM outperforms state-of-the-art HLS-compatible DMM solutions by 61.69%∼99.99% in performance improvement and 23.79%∼97.22% in resource consumption savings. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Memory management

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Differentially Private Deep Learning with Iterative Gradient Descent Optimization

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ACM/IMS Transactions on Data Science 2021年第4期2卷 1–27页

作者： Ding, Xiaofeng Chen, Lin Zhou, Pan Jiang, Wenbin Jin, Hai National Engineering Research Center for Big Data Technology and System Lab Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Hubei Engineering Research Center on Big Data Security School of Cyber Science and Engineering Huazhong University of Science and Technology Wuhan430074 China

Deep learning has achieved great success in various areas and its success is closely linked to the availability of massive data. But in general, a large dataset could include sensitive data and therefore the model should have the capability to avoid privacy leakage. To achieve this aim, many works apply the famous privacy framework named differential privacy into deep learning to preserve privacy. In this article, we propose a novel perturbed iterative gradient descent optimization (PIGDO) algorithm and prove that this algorithm satisfies the differential privacy. Besides, we propose a modified moments accountant (MMA) method to conduct the privacy analysis and obtain a tighter bound of privacy loss compared with the original moments accountant method. A number of experiments demonstrate that our optimization algorithm can not only improve the model accuracy and training speed, but also achieve better privacy guarantees over the state-of-the-art algorithm while reaching the equivalent accuracy. We provide codes for all of our experiments in https://***/CGCL-codes/***. © 2022 Association for computing Machinery.

关键词： Large dataset

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Network and Parallel computing 1

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丛书名： Lecture Notes in Computer Science

1000年

作者： Hai Jin Daniel Reed Wenbin Jiang

ISBN: (数字)9783540322467

ISBN: (纸本)9783540298106

These proceedings contain the papers presented at the 2005 IFIP International Conference on Network and Parallel computing (NPC 2005), held in Beijing, China, between November 30 and December 3, 2005. The goal of the conference was to establish an international forum for engineers and scientists to present their ideas and experiences in network and parallel computing. A total of 320 submissions were received in response to our Call for Papers. These papers were from the following countries or regions: Australia, Canada, China, France, Germany, Hong Kong, India, Iran, Italy, Japan, Korea, Lux- burg, Nepal, Netherlands, Taiwan, United Arab Emirates, and United States. Each submission was sent to at least three *** paper was judged - cording to its originality, innovation, readability, and relevance to the expected ***,atotalof68paperswereretainedfor- clusionin *** the 68 papers,48 wereacceptedasfull papers for presentation at the conference. We also accepted 20 papers as short papers for a possible brief presentation at the conference, followed by discussion during a poster session. Thus, only 21% of the total submissions could be included in the ?nal program.

关键词： Theory of Computation Computer Communication Networks Software Engineering Operating systems Algorithm Analysis and Problem Complexity Information systems Applications (incl. Internet)

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Short: CICC: A fine-grained, semantic-aware, and transparent approach to preventing permission leaks for android permission managers 8

Short: CICC: A fine-grained, semantic-aware, and transparent...

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8th ACM Conference on Security and Privacy in Wireless and Mobile Networks, WiSec 2015

作者： Wang, Daibin Yao, Haixia Li, Yingjiu Jin, Hai Zou, Deqing Deng, Robert H. Services Computing Technology and System Lab. Cluster and Grid Computing Lab. School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Information Systems Singapore Management University Singapore

ISBN: (纸本)9781450336239

Android's permission system offers an all-or-nothing installation choice for users. To make it more flexible, users may choose a popular app tool, called permission manager, to selectively grant or revoke an app's permissions at runtime. A fundamental requirement for such permission manager is that the granted or revoked permissions should be enforced faithfully. However, we discover that none of existing permission managers meet this requirement due to permission leaks. To address this problem, we propose CICC, a finegrained, semantic-aware, and transparent approach for any permission managers to defend against the permission leaks. Compared to existing solutions, CICC is fine-grained because it detects the permission leaks using call-chain information at the component instance level, instead of at the app level or component level. The fine-grained feature enables it to generate a minimal impact on the usability of running apps. CICC is semantic-aware in a sense that it manages call-chains in the whole lifecycle of each component instance. CICC is transparent to users and app developers, and it requires minor modification to permission managers. Our evaluation shows that CICC incurs relatively low performance overhead and power consumption. Copyright 2015 ACM.

关键词： Android Call-chain Permission leaks Permission manager

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RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference 24

RTGA: A Redundancy-free Accelerator for High-Performance Tem...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Yu, Hui Zhang, Yu Tan, Andong Lu, Chenze Zhao, Jin Liao, Xiaofei Jin, Hai Liu, Haikun National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China

ISBN: (纸本)9798400706011

Temporal Graph Neural Network (TGNN) has attracted much research attention because it can capture the dynamic nature of complex networks. However, existing solutions suffer from redundant computation overhead and excessive off-chip communications for TGNN inference because they often rely on redundant graph sampling and repeatedly fetching the features and vertex memory. This paper proposes a redundancy-free accelerator, RTGA, for high-performance TGNN inference. Specifically, RTGA proposes a redundancy-aware execution approach with temporal tree into a novel accelerator design to effectively eliminate unnecessary data processing for fewer redundant computations and off-chip communications and also designs a temporal-aware data caching method to improve data locality for TGNN. We have implemented and evaluated RTGA on a Xilinx Alveo U280 FPGA card. Compared with cutting-edge software solutions (i.e., TGN and TGL) and hardware solutions (i.e., BlockGNN and FlowGNN), RTGA improves the performance of TGNN inference by an average of 473.2x, 87.4x, 8.2x, and 6.9x and saves energy by 542.8x, 102.2x, 9.4x, and 8.3x, respectively. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Spatio-temporal data

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FedRKG: A Privacy-Preserving Federated Recommendation Framework via Knowledge Graph Enhancement 18th

FedRKG: A Privacy-Preserving Federated Recommendation Framew...

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18th International Conference on Green, Pervasive, and Cloud computing, GPC 2023

作者： Yao, Dezhong Liu, Tongtong Cao, Qi Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China School of Computing Science University of Glasgow Glasgow United Kingdom

ISBN: (纸本)9789819998951

Federated Learning (FL) has emerged as a promising approach for preserving data privacy in recommendation systems by training models locally. Recently, Graph Neural Networks (GNN) have gained popularity in recommendation tasks due to their ability to capture high-order interactions between users and items. However, privacy concerns prevent the global sharing of the entire user-item graph. To address this limitation, some methods create pseudo-interacted items or users in the graph to compensate for missing information for each client. Unfortunately, these methods introduce random noise and raise privacy concerns. In this paper, we propose FedRKG, a novel federated recommendation system, where a global knowledge graph (KG) is constructed and maintained on the server using publicly available item information, enabling higher-order user-item interactions. On the client side, a relation-aware GNN model leverages diverse KG relationships. To protect local interaction items and obscure gradients, we employ pseudo-labeling and Local Differential Privacy (LDP). Extensive experiments conducted on three real-world datasets demonstrate the competitive performance of our approach compared to centralized algorithms while ensuring privacy preservation. Moreover, FedRKG achieves an average accuracy improvement of 4% compared to existing federated learning baselines. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd 2024.

关键词： Recommender systems

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D-overlay: A delay-aware overlay for gaming services

D-overlay: A delay-aware overlay for gaming services

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3rd International Conference on Innovative computing Information and Control, ICICIC'08

作者： Xiaofei, Liao Linchen, Yu Hai, Jin Hong, Yao Cluster and Grid Computing Lab. Services Computing Technology and System Lab. Huazhong University of Science and Technology Wuhan 430074 China School of Computer Science and Technology China University of Geosciences Wuhan 430074 China

ISBN: (纸本)9780769531618

Peer-to-peer (P2P) has become an important computing model because of its adaptation, selforganization and autonomy. But how to organize dynamic nodes in P2P networks efficiently for gaming message passing services is still a challenge. This paper present an approach, named D-overlay, a delay-aware overlay for gaming services, to implement node clustering based on link delay of nodes communications in the P2P network. This approach measures the delays among peers, explores the node connectivity together with the connection quality. Then, it builds a service ring for each peer according to its latency status, and keeps the low latency among neighbors by periodical adjustments. D-overlay improves the extensibility and reliability. One system, called PKTown, has been deployed based on D-overlay in CERNET of China. © 2008 IEEE.

关键词： Message passing

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