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MalScan: Android Malware Detection Based on Social-Network Centrality Analysis

IEEE Transactions on Dependable and Secure computing 2025年

作者： Wu, Yueming Suo, Wenqi Feng, Siyue Zou, Deqing Yang, Wei Liu, Yang Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Hubei Engineering Research Center on Big Data Security School of Cyber Science and Engineering Wuhan430074 China Jinyinhu Laboratory Wuhan430074 China University of Texas at Dallas United States Nanyang Technological University Singapore Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China

Malware scanning of an app market is expected to be scalable and effective. However, existing approaches use syntax-based features that can be evaded by transformation attacks or semantic-based features which are usually extracted by expensive program analysis. Therefore, to address the scalability challenges of traditional heavyweight static analysis, we propose a graph-based lightweight approach MalScan for Android malware detection. MalScan considers the function call graph as a complex social network and employs centrality analysis on sensitive application program interfaces (APIs) to express the semantic characteristics of the graph. On this basis, machine learning algorithms and ensemble learning algorithms are applied to classify the extracted features. We evaluate MalScan on datasets of 104,892 benign apps and 108,640 malwares, and the results of experiments indicate that MalScan outperforms six state-of-the-art detectors and can quickly detect Android malware with an f-value as high as 99%. In addition, there are also significant improvements in the robustness of Android app evolution and robustness to obfuscation. Finally, we conduct an exhaustive statistical study of over one million applications in the Google-Play app market and successfully identify 498 zero-day malware, which further validates the feasibility of MalScan on market-wide malware scanning. © 2004-2012 IEEE.

关键词： Android malware

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Heterogeneous differential privacy for vertically partitioned databases

Heterogeneous differential privacy for vertically partitione...

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作者： Xia, Yang Zhu, Tianqing Ding, Xiaofeng Jin, Hai Zou, Deqing National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Deakin University Victoria Australia

Existing privacy-preserving approaches are generally designed to provide privacy guarantee for individual data in a database, which reduces the utility of the database for data analysis. In this paper, we propose a novel differential privacy mechanism to preserve the heterogeneous privacy of a vertically partitioned database based on attributes. We first present the concept of privacy label, which characterizes the privacy information of the database and is instantiated by the classification. Then, we use an information-based method to systematically explore the dependencies between all attributes and the privacy label. We finally assign privacy weights to every attribute and design a heterogeneous mechanism according to the basic Laplace mechanism. Evaluations using real datasets demonstrate that the proposed mechanism achieves a balanced privacy and utility. © 2019 John Wiley & Sons, Ltd.

关键词： Database systems

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FedAA: A Reinforcement Learning Perspective on Adaptive Aggregation for Fair and Robust Federated Learning

arXiv

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arXiv 2024年

作者： He, Jialuo Chen, Wei Zhang, Xiaojin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China School of Microelectronics and Communication Engineering Chongqing University Chongqing400044 China School of Software Engineering Huazhong University of Science and Technology Wuhan430074 China

Federated Learning (FL) has emerged as a promising approach for privacy-preserving model training across decentralized devices. However, it faces challenges such as statistical heterogeneity and susceptibility to adversarial attacks, which can impact model robustness and fairness. Personalized FL attempts to provide some relief by customizing models for individual clients. However, it falls short in addressing server-side aggregation vulnerabilities. We introduce a novel method called FedAA, which optimizes client contributions via Adaptive Aggregation to enhance model robustness against malicious clients and ensure fairness across participants in non-identically distributed settings. To achieve this goal, we propose an approach involving a Deep Deterministic Policy Gradient-based algorithm for continuous control of aggregation weights, an innovative client selection method based on model parameter distances, and a reward mechanism guided by validation set performance. Empirically, extensive experiments demonstrate that, in terms of robustness, FedAA outperforms the state-of-the-art methods, while maintaining comparable levels of fairness, offering a promising solution to build resilient and fair federated systems. Our code is available at https://***/Gp1g/FedAA. Copyright © 2024, The Authors. All rights reserved.

关键词： Federated learning

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RAHP: A Redundancy-aware Accelerator for High-performance Hypergraph Neural Network

RAHP: A Redundancy-aware Accelerator for High-performance Hy...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Hui Yu Yu Zhang Ligang He Yingqi Zhao Xintao Li Ruida Xin Jin Zhao Xiaofei Liao Haikun Liu Bingsheng He Hai Jin National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Department of Computer Science University of Warwick United Kingdom National University of Singapore Singapore

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Hypergraph Neural Network (HyperGNN) has emerged as a potent methodology for dissecting intricate multilateral connections among various entities. Current software/hardware solutions leverage a sequential execution model that relies on hyperedge and vertex indices for conducting standard matrix operations for HyperGNN inference. Yet, they are impeded by the dual challenges of redundant computation and irregular memory access overheads. This is primarily due to the frequent and repetitive access and updating of a number of feature vectors corresponding to the same hyperedges and vertices. To address these challenges, we propose the first redundancy-aware accelerator, RAHP, which enables high performance execution of HyperGNN inference. Specifically, we present a redundancy-aware asynchronous execution approach into the accelerator design for HyperGNN to reduce redundant computations and off-chip memory accesses. To unveil opportunities for data reuse and unlock the parallelism that existing HyperGNN solutions fail to capture, it prioritizes vertices with the highest degree as roots, prefetching other vertices along the hypergraph structure to capture the common vertices among multiple hyperedges, and synchronizing the computations of hyperedges and vertices in real-time. By such means, this facilitates the concurrent processing of relevant hyperedge and vertex computations of the common vertices along the hypergraph topology, resulting in smaller redundant computations overhead. Furthermore, by efficiently caching intermediate results of the common vertices, it curtails memory traffic and off-chip communications. To fully harness the performance potential of our proposed approach in the accelerator, RAHP incorporates a topology-driven data loading mechanism to minimize off-chip memory accesses on the fly. It is also endowed with an adaptive data synchronization scheme to mitigate the effects of conflicting updates of both hyperedges and vertices. Moreover, RAHP emplo

关键词： Computational modeling Neural networks Memory management Loading Energy conservation Vectors Software Topology Synchronization Standards

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CPSAA: Accelerating Sparse Attention using Crossbar-based Processing-In-Memory Architecture

arXiv

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arXiv 2022年

作者： Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei Huang, Yu Liu, Cong Xu, Jiahong Duan, Zhuohui Chen, Dan Gui, Chuangyi National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The attention-based neural network attracts great interest due to its excellent accuracy enhancement. However, the attention mechanism requires huge computational efforts to process unnecessary calculations, significantly limiting the system’s performance. To reduce the unnecessary calculations, researchers propose sparse attention to convert some dense-dense matrices multiplication (DDMM) operations to sampled dense-dense matrix multiplication (SDDMM) and sparse matrix multiplication (SpMM) operations. However, current sparse attention solutions introduce massive off-chip random memory access since the sparse attention matrix is generally unstructured. We propose CPSAA, a novel crossbar-based processing-in-memory (PIM)-featured sparse attention accelerator to eliminate off-chip data transmissions. First, we present a novel attention calculation mode to balance the crossbar writing and crossbar processing latency. Second, we design a novel PIM-based sparsity pruning architecture to eliminate the pruning phase’s off-chip data transfers. Finally, we present novel crossbar-based SDDMM and SpMM methods to process unstructured sparse attention matrices by coupling two types of crossbar arrays. Experimental results show that CPSAA has an average of 89.6×, 32.2×, 17.8×, 3.39×, and 3.84× performance improvement and 755.6×, 55.3×, 21.3×, 5.7×, and 4.9× energy-saving when compare with GPU, FPGA, SANGER, ReBERT, and ReTransformer. Copyright © 2022, The Authors. All rights reserved.

关键词： Memory architecture

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Design and Simulation of Multi-tiered Heterogeneous Memory Architecture

Design and Simulation of Multi-tiered Heterogeneous Memory A...

引用

International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems (MASCOTS)

作者： Jinyuan Hu Haikun Liu Hai Jin Xiaofei Liao National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Heterogeneous memory systems have become increasingly popular in recent years. Because heterogeneous storage media often show significantly different characteristics in terms of bandwidth, latency, capacity, and energy consumption, it is still challenging to best utilize them for cost-efficient and energy-efficient heterogeneous memory systems. In this paper, we propose a simulation framework for multi-tiered heterogeneous memory architectures based on GEM5 and DRAMsim3 simulators. We design a heterogeneous memory controller to architect Non-Volatile Memory (NVM) as main memory, and architect both Dynamic Random Access Memory (DRAM) and High-Bandwidth Memory (HBM) as a hybrid cache of NVM. Specifically, HBM, DRAM, and NVM are managed in a single (flat) address space. However, we use an address remapping table to maintain the mappings between NVM pages and HBM/DRAM pages, and logically manage HBM/DRAM/NVM as a three-tiered hybrid memory system. We also design a hardware-supported hot page monitor based on Majority Element Algorithm (MEA) to identify the hottest pages in the DRAM, and a dynamic threshold adjustment scheme for hot page migration to balance the memory bandwidth between DRAM and HBM. Our multi-tiered heterogeneous memory architecture can take advantage of the large capacity of NVM, the low latency of DRAM, and the high bandwidth of HBM concurrently. Experimental results show that our tiered memory architecture can improve application performance by an average of $2.5\times$ compared with an NVM-only architecture, and up to 57.4% compared with a DRAM-only architecture. Moreover, the performance gap between our HBM/DRAM/NVM architecture and a HBM-only architecture is less than 10%.

关键词： Analytical models Nonvolatile memory Heuristic algorithms Computational modeling Memory architecture Random access memory Computer architecture

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Fast and Scalable Gate-Level Simulation in Massively Parallel systems

Fast and Scalable Gate-Level Simulation in Massively Paralle...

引用

IEEE International Conference on Computer-Aided Design

作者： Haichuan Hu Zichen Xu Yuhao Wang Fangming Liu Services Computing Technology and System Lab Cluster and Grid Computing Lab National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Mathematics and Computer Science Nanchang University Nanchang China Pengcheng Laboratory Shenzhen China

The natural bijection between a proposed circuit design and its graph representation shall allow any graph optimization algorithm deploying into many-core systems efficiently. However, this process suffers from the exponentially growing overhead and heavy memory footprint with the signal propagation. To conquer the unique challenge, we systematically study the simulation with millions of gates, and identify that the processing complexity could grow exponentially from the signal inputs, the skewness of the computational graph stays. Thus, we present ZhouBi, a fast and scalable gate-level simulation framework to fully exploit the parallelism from many-core systems. ZhouBi contributes in threefolds, (I) a graph representation that colors gate-level netlists and identifies skew partitions based on the graph skewness; (II) A set of heuristic algorithms that picks opportunistic and conservative algorithms to accelerate the simulation; (III) A system facility that supports selective mapping between simulation and many-core, providing a tradeoff between the risk of concurrent simulation fail and performance gain. We have prototyped ZhouBi and evaluated it with practical baselines. ZhouBi can achieve a 27.6× performance gain, as compared to the state-of-the-practice Veriwell without compromising any correctness. Our framework supports large graphs enabling scale-out gate-level simulations for chip design.

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Variational Bayes for Federated Continual Learning

arXiv

引用

arXiv 2024年

作者： Yao, Dezhong Li, Sanmu Dai, Yutong Xu, Zhiqiang Hu, Shengshan Zhao, Peilin Sun, Lichao The National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab. Cluster and Grid Computing Lab. School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Lehigh University PA18015 United States Mohamed bin Zayed University of Artificial Intelligence United Arab Emirates Tencent AI Lab. Shenzhen China

Federated continual learning (FCL) has received increasing attention due to its potential in handling real-world streaming data, characterized by evolving data distributions and varying client classes over time. The constraints of storage limitations and privacy concerns confine local models to exclusively access the present data within each learning cycle. Consequently, this restriction induces performance degradation in model training on previous data, termed "catastrophic forgetting". However, existing FCL approaches need to identify or know changes in data distribution, which is difficult in the real world. To release these limitations, this paper directs attention to a broader continuous framework. Within this framework, we introduce Federated Bayesian Neural Network (FedBNN), a versatile and efficacious framework employing a variational Bayesian neural network across all clients. Our method continually integrates knowledge from local and historical data distributions into a single model, adeptly learning from new data distributions while retaining performance on historical distributions. We rigorously evaluate FedBNN’s performance against prevalent methods in federated learning and continual learning using various metrics. Experimental analyses across diverse datasets demonstrate that FedBNN achieves state-of-the-art results in mitigating forgetting. Copyright © 2024, The Authors. All rights reserved.

关键词： Digital storage

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Hyperbit: A Financial Temporal Knowledge Graph Data Storage system

SSRN

引用

SSRN 2022年

作者： Yuan, Pingpeng Han, Sheng Zang, Shaoqi Shi, Xuanhua Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

In the field of finance, data has the characteristics of temporal multi-frequency and heterogeneous high dimension, and the traditional knowledge graph is not suitable to express the temporal relation of financial data, so the financial temporal knowledge graph has become a research hotspot recently. There are a large number of temporal edges in the financial temporal knowledge graph. The use of general graph database management system to store financial knowledge graph data has problems such as large storage scale and slow update speed, and it cannot realize the traceability of financial data, so it cannot meet the needs of the financial field. In order to solve these problems, HyperBit, a storage system for efficient storage and management of financial data, is designed and implemented. Firstly, a temporal quad storage structure is proposed. Secondly, the Log Structured Cumulative Update (LSCU) is proposed to update financial temporal data efficiently. The update log module is designed in the system. When there is data to update, it is not directly updated in the data storage of the system, but recorded in the update log, and the system updates the content of the update log cumulatively. The system manages update logs by partition and chunk, which makes the log storage compact and independent. Besides, it is convenient for parallel processing and it improves the data update speed. Thirdly, a Bidirectional Backtracking by Final and Optimal Root (BBFOR) method is proposed to meet the requirements of efficient traceability of financial data. Unlike traditional version tracing method, BBFOR adopt both the snapshot and incremental methods which balance the space and time cost of version switching, and BBROF consider the version of the access frequency characteristic and set up the final root and the optimal root. Besides, BBROF adopt bidirectional backtracking technology to improve the efficiency of the version switching. Experimental results show that the storage cost

关键词： Switching

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Reconciling Selective Logging and Hardware Persistent Memory Transaction

Reconciling Selective Logging and Hardware Persistent Memory...

引用

IEEE Symposium on High-Performance Computer Architecture

作者： Chencheng Ye Yuanchao Xu Xipeng Shen Yan Sha Xiaofei Liao Hai Jin Yan Solihin National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China North Carolina State University Raleigh North Carolina USA University of Central Florida Florida USA

Log creation, maintenance, and its persist ordering are known to be performance bottlenecks for durable transactions on persistent memory. Existing hardware persistent memory transactions overlook an important opportunity for improving performance: some persistent data is algorithmically redundant such that it can be recovered from other data, removing the need for logging such data. The paper presents an ISA extension that enables selective logging for hardware persistent memory transactions for the first time. The ISA extension features two novel components: fine-grain logging and lazy persistency. Fine-grain logging allows hardware to log updates on data in the granularity of words without lengthening the critical path of data accesses. Lazy persistency allows updated data to remain in the cache after the transaction commits. Together, the new hardware persistent memory transaction outperforms the state-of-the-art hardware counterpart by 1.8× on average.

关键词： Computer architecture Maintenance engineering Hardware Optimization IEEE transactions

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