In a Wireless Sensor Networks (WSN), there are normally one or several sensor nodes working as Access Points (AP), which are able to provide a relay for other sensors to an external Internet connection. Since WSNs are...
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COQ is an interactive theorem proving tool. The paper abstractly describes the feature of COQ, the architecture and working modes of PLC program with the example of typical PLC. It also introduces the first-order logi...
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COQ is an interactive theorem proving tool. The paper abstractly describes the feature of COQ, the architecture and working modes of PLC program with the example of typical PLC. It also introduces the first-order logic syntax and semantics of Intuitionistic Logic. It briefly introduces the main Gallina language syntax elements, the corresponding use methods and main theorem proving tactic on COQ. The work has modeled kernel data type and basic statements and and the denotational semantics of PLC program with Gallina. It has given the correctness proof of PLC program based on theorem proving, i.e. based on semantics function the relationship of configuration between the before codes execution and the after is proved. The main purpose is to prove whether a PLC program satisfies certain nature within a scan period.
Compared with the CSG-based approach, the Brep-based approach has several advantages to construct 3D models from 2D engineering drawings, such as the structure is simpler and the domain of objects that can be handled ...
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Pseudo recognition is essential to reconstruct correct 3D models from engineering drawings. This paper proposes a novel linear algorithm to recognize pseudo elements based on the existence of non-manifold edges. First...
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This paper introduces a two-stage Linear Logic based program synthesis approach to automatic RESTful web service composition. The Linear Logic theorem proof is applied at both resource and service invocation method le...
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As the technique developing, some important problems in storage systems have been solved appropriately. A good example is the development of RAID-6 code techinque, the appear of it has greatly improved the reliability...
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As the technique developing, some important problems in storage systems have been solved appropriately. A good example is the development of RAID-6 code techinque, the appear of it has greatly improved the reliability, availability of modern storage systems. Some best known vertical RAID-6 code like P-code and X-code has acquire optimal or near optimal performance in encoding, decoding and update. But they do not detailedly analysis the status of reconstruction with single-disk failure. In the status, there are many paths to perform reconstructing. But the path you choice will greatly affect the performance of whole storage system. Based the phenomenon found above, we present a fast and effcient scheme, Path Directed Recovery Scheme (PDRS for short), to find a optimal path to reconstruct single-disk failure in P-code and X-code. Using PDRS, we will acquire some benefits: (1) it can decrease the disk I/O complexity caused by reconstruction and therefore accelerating the speed of reconstruction, (2) it can balance the load on each disk, consequently can avoid the hot problem in a degree. We perform theoretical analysis and evaluation of the PDRS when applied in P-code with (p-1)-disk and X-code with p-disk. Our theoretical analysis shows that PDRS applied in P-code with (p-1)-disk can acquire up to 25% performance improvement. To verify the effectiveness of PDRS, we have conducted intenvice simulation. The simulation results shows that PDRS applied in P-code with (p-1)-disk can speedup the recovery duration by up to 23.6% under spare-rebuilding mode. Overall, PDRS is a efficient and useful recovery scheme that can applied to all of the vertical RAID-6 code.
A Social network graph shows social interactions and relationships between individuals in a specific social environment, which is very helpful for analyzing social relationships, activities, structures, etc. The autho...
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The quality of virtual view based on multi-view video (MVD) plus depth format is often evaluated by PSNR or subjectively judged. However, due to synthesizing arbitrary view images, the virtual view images mostly hav...
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The quality of virtual view based on multi-view video (MVD) plus depth format is often evaluated by PSNR or subjectively judged. However, due to synthesizing arbitrary view images, the virtual view images mostly have no reference images and are only assessed using non-reference. Virtual view images synthesized by depth estimation reference software (DERS) and view synthesis reference software (VSRS) often accompanied with blockiness and other distortions on the edge. In addition, matching level for the depth map and the corresponding texture maps of left and right views also affects the quality of the virtual view. This paper compares the edge similarity of the depth and the corresponding texture maps which generate the intermediate virtual view and combined with the virtual view's blockiness which causing blur to evaluate the quality of the virtual view. Experiment results show that the proposed method can reflect the quality of the virtual view better.
To find the best memory system for emerging workloads, traces are obtained during application's execution, then caches with different configurations are simulated using these traces. Since program traces can be se...
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To find the best memory system for emerging workloads, traces are obtained during application's execution, then caches with different configurations are simulated using these traces. Since program traces can be several gigabytes, simulation of cache performance is a time consuming process. Compute unified device architecture (CUDA) is a software development platform which enables programmers to accelerate the general-purpose applications on the graphics processing unit (GPU). This paper presents a real time multi-core cache simulator, which was built based on the Pin tool to get the memory reference, and fast method for multi-core cache simulation using the CUDA-enabled GPU. The proposed method is accelerated by the following techniques: execution parallelism exploration, memory latency hiding, a novel trace compression methodology. We describe how these techniques can be incorporated into CUDA code. Experimental results show that the hybrid parallel method of time-partitioning combines with set-partitioning presented here is 11.10× speedup compared to the CPU serial simulation algorithm. The present simulator can characterize cache performance of single-threaded or multi-threaded workloads at the speeds of 6-15 MIPS. It can simulates 6 cache configurations within one single pass at this speeds compared to CMP$im, which can only simulate one cache configuration each simulation pass at the speeds of 4-10 MIPS.
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