Electromagnetic Brain Imaging consists of the mapping of neural generators of magnetic fields and electric potentials measured outside the head using Magnetoencephalography (MEG) and Electroencephalography (EEG), resp...
详细信息
A new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode si...
详细信息
A new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode sign.l rejection capability. Using 0.35μm CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a - 54.6dB total harmonic distortion (THD) and more than 1 GHz - 3dB bandwidth. A 3rd order elliptic low pass gm-C filter with a cutoff frequency of 150MHz is demonstrated as an application of the new transconductor.
In this paper, an efficient semi-systolic array architecture for separable 2-D Discrete Wavelet Transform (DWT) is introduced. The semi-systolic array is applicable to any convolution that requires an arbitrary subsam...
In this paper, an efficient semi-systolic array architecture for separable 2-D Discrete Wavelet Transform (DWT) is introduced. The semi-systolic array is applicable to any convolution that requires an arbitrary subsampling function. The semi-systolic array presents a better implementation of the convolution function of DWT. This kind of implementation offers a higher efficiency compared to regular systolic implementation when applied for 2-D DWT. The architecture has an efficiency of at least 91% which increases proportional to the number of octaves with no change in the architecture design except for minor modifications to the control logic and memory size. The propose architecture is scalable for different size of filter and different number of octave. The communication routing is minimum since data transfers are limited to immediate neighboring processors. The components of the architecture are fairly regular and consist of minimum number of computational units which makes it a good candidate for vlsi implementation.
暂无评论