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Smartphone-Based Real-Time Digital signal processing

2015年

作者： Nasser Kehtarnavaz Shane Parris Abhishek Sehgal

ISBN: (数字)9781627058179

Real-time or applied digital signal processing courses are offered as follow-ups to conventional or theory-oriented digital signal processing courses in many engineering programs for the purpose of teaching students the technical know-how for putting signal processing algorithms or theory into practical use. These courses normally involve access to a teaching laboratory that is equipped with hardware boards, in particular DSP boards, together with their supporting software. A number of textbooks have been written discussing how to achieve real-time implementation on these hardware boards. This book discusses how smartphones can be used as hardware boards for real-time implementation of signal processing algorithms as an alternative to the hardware boards that are currently being used in signal processing teaching laboratories. The fact that mobile devices, in particular smartphones, have now become powerful processing platforms has led to the development of this book, thus enabling students to use their own smartphones to run signal processing algorithms in real-time considering that these days nearly all students possess smartphones. Changing the hardware platforms that are currently used in applied or real-time signal processing courses to smartphones creates a truly mobile laboratory experience or environment for students. In addition, it relieves the cost burden associated with using a dedicated signal processing board noting that the software development tools for smartphones are free of charge and are well-developed. This book is written in such a way that it can be used as a textbook for applied or real time digital signal processing courses offered at many universities. Ten lab experiments that are commonly encountered in such courses are covered in the book. This book is written primarily for those who are already familiar with signal processing concepts and are interested in their real-time and practical aspects. Similar to existing real-time courses, know

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Deep Generative Models for Bayesian Inference on High-Rate Sensor Data: Applications in Automotive Radar and Medical Imaging

arXiv

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arXiv 2025年

作者： Stevens, Tristan S.W. Overdevest, Jeroen Nolan, Oisín van Nierop, Wessel L. van Sloun, Ruud J.G. Eldar, Yonina C. Department of Electrical Engineering University of Technology Eindhoven Netherlands Signal Processing Algorithms NXP Semiconductors Netherlands Faculty of Mathematics and Computer Science Weizmann institute of Science Israel

Deep generative models have been studied and developed primarily in the context of natural images and computer vision. This has spurred the development of (Bayesian) methods that use these generative models for inverse problems in image restoration, such as denoising, inpainting, and super-resolution. In recent years, generative modeling for Bayesian inference on sensory data has also gained traction. Nevertheless, the direct application of generative modeling techniques initially designed for natural images on raw sensory data is not straightforward, requiring solutions that deal with high dynamic range signals acquired from multiple sensors or arrays of sensors that interfere with each other, and that typically acquire data at a very high rate. Moreover, the exact physical data-generating process is often complex or unknown. As a consequence, approximate models are used, resulting in discrepancies between model predictions and the observations that are non-Gaussian, in turn complicating the Bayesian inverse problem. Finally, sensor data is often used in real-time processing or decision-making systems, imposing stringent requirements on, e.g., latency and throughput. In this paper, we will discuss some of these challenges and offer approaches to address them, all in the context of high-rate real-time sensing applications in automotive radar and medical imaging. © The Authors. Published by the Royal Society under the terms of the Creative Commons Attribution License http://***/licenses/by/4.0/, which permits unrestricted use, provided the original author and source are credited. © 2025, CC BY-SA.

关键词： Inverse problems

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signal Reconstruction for FMCW Radar Interference Mitigation Using Deep Unfolding 48

Signal Reconstruction for FMCW Radar Interference Mitigation...

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48th IEEE International Conference on Acoustics, Speech and signal processing, ICASSP 2023

作者： Overdevest, J. Koppelaar, A.G.C. Bekooij, M.J.G. Youn, J. Sloun, R.J.G. Van Nxp Semiconductors Signal Processing Algorithms Eindhoven Netherlands Eindhoven University of Technology Dept. of Electrical Engineering Eindhoven Netherlands

ISBN: (纸本)9781728163277

Removal of frequency-modulated continuous wave (FMCW) interference by zeroing corrupted samples causes significant distortions and peak power losses in the range-Doppler map. Existing methods aim to diminish these distortions by utilizing data from one dimension to reconstruct the corrupted samples, which do not perform well when a large number of samples are interfered and have diﬃculty recovering weak target *** this paper, model-based deep learning interference mitigation algorithms, called ALISTA and ALFISTA, are presented that reduce these artifacts by leveraging the full integration gain using all uncorrupted fast-time and slow-time samples. Simulations with 50% corrupted samples show that target peak power loss and velocity peak-to-sidelobe ratio (VPSR) with a 20-layer ALFISTA improves with 5.5 and 9.6 dB compared to zeroing. Furthermore, significant improvements in precision and recall are observed, even when large amounts (50-80%) of samples are missing. © 2023 IEEE.

关键词： signal reconstruction

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Iterative suppression of co-channel interference

Iterative suppression of co-channel interference

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17th European signal processing Conference, EUSIPCO 2009

作者： Nisar, M. Danish Nottensteiner, Hans Utschick, Wolfgang Technical University Munich Institute for Signal Processing Munich Germany Nokia Siemens Networks Radio Access Algorithms and Simulations Munich Germany

Co-Channel Interference (CCI) is one of the major bottlenecks in the performance of today's densely planned wireless cellular systems. A receiver equipped with multiple receive antennas and sufficient computational budget typically exploits the spatial dimension and iterative processing between the detector and the channel decoder to suppress this interference. In this paper, we propose modifications in the standard iterative turbo processing based CCI suppression to especially boost the receiver performance in a dominant CCI scenario. Performance gains of 3-5 dB are shown to be achieved over the conventional iterative approaches for an LTE uplink system. © EURASIP, 2009.

关键词： Receiving antennas

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Architectural Requirements of Parallel Computational Biology Applications with Explicit Instruction Level Parallelism 20

Architectural Requirements of Parallel Computational Biology...

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20th International Conference on Parallel and Distributed Computing Systems, PDCS 2007

作者： Azeemi, Naeem Z. Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms Institute of Communications and Radio Frequency Engineering University of Technology Vienna Austria

ISBN: (纸本)9781604233926

Computational biology applications expression profile is a critical performance metric in high end genomic data processing. These profiles are compute intensive and offers a wide range of computation pattern ranging from data base searching applications to highly irregular phylogenetic trees. Such debilitating factors lead to poor architecture-application correlation. A prior knowledge of software application would be very useful to exploit the instruction level parallelism inside the computational biology applications. This paper presents an integrated approach for parameterized workload characterization and trace driven simulation at a high end multimedia processor in bioinformatics applications. A set of sixteen widely used bioinformatics applications is selected as benchmark. Software monitoring techniques are used to collect execution traces. Based on the measured results, we investigate both the computation and communication behavior of these applications, including execution time, functional unit utilization, scheduling factors and cache misses. The temporal and spatial localities in gnomic data are also discussed. Experimental results are measured at a high end SIMD (single instruction stream over multiple data stream) processor. © 20th International Conference on Parallel and Distributed Computing Systems, PDCS 2007. All rights reserved.

关键词： Application programs

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Evaluation of Architectural Support for Speech Codecs Application in Large-Scale Parallel Machines 20

Evaluation of Architectural Support for Speech Codecs Applic...

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20th International Conference on Parallel and Distributed Computing Systems, PDCS 2007

作者： Azeemi, Naeem Zafar Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms Institute of Communications and Radio Frequency Engineering University of Technology Vienna Gusshausstrasse 25/389 ViennaA-1040 Austria

ISBN: (纸本)9781604233926

Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have very large instruction foot prints and consequently stalled due to instruction cache misses. The conflicts in on-chip caches contribute a large fraction of the CPU cycle penalty and hence increase in power consumption. Many commercial tools are developed to minimize such cache misses by adequately placing the frequently called procedures in an application. Followed by profile extraction, these tools use cache line coloring and post compilation techniques for cache hit optimization. The major impediment in the optimal performance of such tools is their static layout profile, which does not consider the dynamic behavior of the application. We propose a methodology called DCP (dynamic code placement) for positioning code at run time for good instruction cache performance and have implemented in high end processors. The dynamic application profile is completely transparent to the developer’s code. This technique optimizes the code footprint in memory layout of a program. It improves i-cache mapping to increase the number of cache hits and eventually reduce the CPU stalls. Our optimization is powered with static as well as detail run time profile information that extracts the relevant, temporal behavior of the applications. Moreover, while mapping code in instruction cache, the effect of inter-procedural code positioning is also considered. Improvement over the Pettis and Hansen approach (PH) is also shown in results. Though majority of multimedia applications can be optimized by our framework, application dominated with the function pointers do not work correctly. The technique incurs low overheads and enhances the cache hits architecture correlation. For a range of applications we show that instruction miss rates can be reduced by 19-68%. Using a simple model this corresponds to execution time re

关键词： Embedded systems

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Architecture-Aware Hierarchical Probabilistic Source Optimization 19

Architecture-Aware Hierarchical Probabilistic Source Optimiz...

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19th International Conference on Parallel and Distributed Computing Systems, PDCS 2006

作者： Azeemi, N.Z. Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms Institute of Communications and Radio Frequency Engineering University of Technology Vienna Gusshausstrasse 25/389 ViennaA-1040 Austria

ISBN: (纸本)9781604236446

This paper focuses on architecture-aware source-level code transformation methods for low energy consumption in complex VLIW processors. Though energy issue has long been addressed at hardware level, but a significant contribution of software applications can not be ignored. Successive energy-cycle cost guarded parametric optimization are applied in proposed iterative compilation environment to evaluate an application expression profile on complex multimedia processors. The optimization is based on a multi objective function. The constraints of this objective function are formulated using a penalty method;a genetic algorithm finds solutions eventually. The proposed new code transformation methodology determines appropriate parameters for compiler optimization in order to satisfy user constraints on code size, energy, execution time and optimal target architecture usage. The set of experiments presented here characterize the newly introduced approach, while giving an idea about the architecture-based energy-cycle performance issues. Experimental results show that our approach reduces cache misses by an average of 33% (max. 67%), improves typically energy dissipation up to 23% and CPU performance up to 80% for an MPEGdec video algorithm. The approach is general and can easily be integrated in multimedia processor compilers. © 19th International Conference on Parallel and Distributed Computing Systems 2006, PDCS 2006. All rights reserved.

关键词： Energy dissipation

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A multiobjective evolutionary approach for constrained joint source code optimization

A multiobjective evolutionary approach for constrained joint...

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19th International Conference on Computer Applications in Industry and Engineering, CAINE 2006

ISBN: (纸本)9781604236750

The synergy of software and hardware leads to efficient application expression profile (AEP) not only in terms of execution time and energy but also optimal architecture usage. We present an architecture-based parametric optimization of 'C' source code for iterative compilation. Successive source-level, code transformations are applied in order to evaluate an application expression profile on complex multimedia processors. The proposed new code transformation methodology determines appropriate parameters for compiler optimization in order to satisfy user constraints on code size, energy, execution time and optimal target architecture usage. The optimization is based on a multicriteria, objective function. The constraints of this objective function are formulated using a penalty method;a genetic algorithm finds solutions eventually. We examined the performance improvement across typical different multimedia applications on a multimedia processor, TM1302 (Philips). Candidate applications include m100, m200, nlivq, MPEG-1, G-721 and H-264L. Experimental results show that our approach reduces cache misses by an average of 36% (max. 71%), improves typically energy dissipation up to 17% and CPU performance up to 60% for an H-264L video codec algorithm. However, the code size tends to be large, which inevitably leads to a larger memory size. The approach is general and can easily be integrated in multimedia processor compilers.

关键词： Energy dissipation

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Handling architecture-application dynamic behavior in set-top box applications

Handling architecture-application dynamic behavior in set-to...

引用

2nd International Conference on Information and Automation, ICIA 2006

ISBN: (纸本)1424405556

Future ubiquitous computing will be consisted of set-top boxes and handheld devices based on enormous computation power and capability to handle multimedia applications workload. Efficient architecture utilization and optimal application binary will be two important performance metrics for these embedded systems. In real-time system, the conventional method of system design cannot be used. In these methods, the cycle and code size are primarily considered, while power dissipation issue is completely ignored, that inevitably lead to expensive cooling mechanism and eventually increase the system overall cost while reducing reliability. An integrated approach that considers energy-cycle performance at architecture as well as application level is essential for energy efficient application development. This paper focuses on distributed optimization paradigm, based on vertical profiling. The proposal is based on enhance local optimization and peer-to-peer (P2F) source code compilation across application build flow. The earlier procedures incorporate additional steps for pre/post profiling during compilation, scheduling and linking phases. This iterative activity is carried out by methods based on wait-for-graphs or profile monitors. These methods introduce a centralized evaluation at source code (for each transformation and monitored parameters during successive approximation). The proposal introduces the asynchronous evaluation in source to source (sts) process. As a result the code transformation do not trapped in local optimization, rather look for global optimization (for both energy and cycle). Methodology is readily adaptable in an iterative compilation environment where application source code is optimized to satisfy user constraints on code size, energy, execution time and optimal target architecture usage. Experimental results show that our approach enhances parallelism upto 38% in G-721 speech codec, increases architecture correlation upto 17% in video transcode

关键词： Real time systems

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Power aware framework for dense matrix operations in multimedia processors

Power aware framework for dense matrix operations in multime...

引用

2005 Pakistan Section Multitopic Conference, INMIC

作者： Azeemi, N. Zafar Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms Institute of Communications and Radio Frequency Engineering University of Technology Vienna Gusshausstrasse 25/389 A-1040 Vienna Austria

ISBN: (纸本)0780394291

In this paper we analyze1 the use of Decision Tree Grafting, Blocking and Loop Unfolding to improve the performance of dense matrix computations on high performance multimedia processors. The analysis focuses on the practical aspects that can be observed when programming on present DSP processor with multilayered memory levels. The problem is studied on the Philips Nexperia processor. The experimental evaluation of the proposed approach results into better exploitation of functional units, memory hierarchy and highway usage of the target processor. The advantages of the proposed interactive code transformation approach are two-folds. First, effort in optimization is spent only when the program measurement (transformation cost) determines that the effort is necessary and potentially beneficial, and only on those portions of the program where the energy/cycle performance payoff appears to be high. Second, by concatenating subsequent energy/cycle profile-driven low level transformations for higher level manipulations, the system will provide the programmer with a powerful toolset. The approach is illustrated using functional unit usage within a VLIW architecture for low power, which improves energy dissipation up to 34% and CPU performance up to 87% for an idct example.

关键词： Energy dissipation

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