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1993 IEEE International Conference on Acoustics, Speech, and signal processing

作者： B. Wang D.M. Rose A.A. Farag E.J. Delp Engineering Mathematics & Computer Science Department Speed Scientific School University of Louisville Louisville KY USA Computer Vision & Image Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA

An empirical measure for the selection of the edge-enhancement Gaussian filter is developed. The Gaussian filter is specified by its standard deviation sigma ; the filter's spatial support is a function of sigma . An estimation procedure for sigma using Fourier analysis is described. The measure is easy to implement and is based totally on the image at hand. Experimental results suggest that this measure can be used as an aid in deciding the Gaussian filter's spatial support, which is needed to enhance the edges. Other equivalent bandwidth definitions can be used to obtain a measure of the frequency spread in the smoothed image (e.g., the mean-square bandwidth).< >

关键词： Gaussian processes Low pass filters Shape Filtering Frequency Mathematics computer science computer vision Image processing Image segmentation

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Critical performance path analysis, and efficient code generation issues, for the Seamless architecture

Critical performance path analysis, and efficient code gener...

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International Symposium on Parallel processing

作者： D.L. Bright S.A. Fineberg B.H. Pease M.L. Roderick S. Sundaram T.L. Casavant Parallel Processing Laboratory Department of Electrical and Computer Engineering University of Iowa Iowa IA USA Numerical Aerodynamic Simulation NASA Ames Research Center CA USA

An analytical study of potential pathological performance areas of the Seamless architecture is presented. Seamless is a latency-tolerant, distributed memory, multiprocessor architecture. A key component of the philosophy of Seamless, however, is the use of standard, commodity components for a large part of the system. A discussion of the unavoidable implementation compromises imposed by this decision is presented, followed by a summary of some optimistic performance studies. Then an analytical study that parameterizes the predicts the worst-case impact of using standard components is provided. Finally, it is shown that these bottlenecks are manageable via careful generation of target machine code so that the optimistic performance studies become realistic expectations for a range of program behaviors and granularities.< >

关键词： Performance analysis computer architecture Hardware Reduced instruction set computing Workstations Costs Aerodynamics Computational modeling Analytical models Numerical simulation

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A morphological wavelet transform

A morphological wavelet transform

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IEEE International Conference on Systems, Man and Cybernetics

作者： H. Cha L.F. Chaparro Advanced TV and Display Laboratory A/V Research & Development Center Samsung Electronics Company Limited Suwon Kyunggi South Korea Real Time Signal Processing Laboratory Department of Electrical Engineering University of Pittsburgh Pittsburgh PA USA

Using adaptive structuring functions, we develop a morphological interpolation that allows a signal representation similar to the given by the wavelet bank of filters. With morphological operators, the interpolation problem is reduced to solving non-linear equations iteratively to get an approximate expansion of a sampled signal in terms of the structuring functions. We obtain a pyramid-like structure to decompose the signal into smoothed and detail components at different scales, just as in the wavelet representation. The use of non-linear filters in our algorithm reduces the computational complexity associated with the decomposition and synthesis. Our representation is valid for one- and two-dimensional signals. In the two-dimensional case, we consider the non-unique ordering of the structuring functions, and the variety of possible sampling, decimation and interpolation procedures. We illustrate our one- and two-dimensional representations by means of examples.< >

关键词： Wavelet transforms Interpolation signal representations Adaptive filters Filter bank Nonlinear equations Iterative algorithms Computational complexity signal synthesis Sampling methods

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A RATIO-INDEPENDENT CYCLIC MULTIPLICATION D/A CONTERVER USING SWITCHED-CURRENT TECHNIQUE

A RATIO-INDEPENDENT CYCLIC MULTIPLICATION D/A CONTERVER USIN...

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International Conference on signal processing(ICSP’93)

作者： Shenghong Wang M.O.Ahmad Center for Signal Processing and Communications Department of Electrical & Computer Engineering Concordia University 1455 de Maisonneuve Blvd.W.MontrealQuebecCanada H3G 1M8

A ratio-independent cyclic multiplication digital-to-analog converter using switched-current technique is *** converter is capable of achieving a high-resolution and a high-accuracy data conversion without requiring any matching of *** converter operates in the current mode,does not require linear capacitors,and works with low supply *** proposed circuit was simulated using *** results are in close agreement with the theoretical predictions.

关键词： cycle A RATIO-INDEPENDENT CYCLIC MULTIPLICATION D/A CONTERVER USING SWITCHED-CURRENT TECHNIQUE

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Automatic transfer from C to flowgraph for multiprocessor DSP implementation

Automatic transfer from C to flowgraph for multiprocessor DS...

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International Conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Z. Wang G. Mirchandani R.B. Pegram Digital Signal Processing Laboratory Departnient of Computer Science and Electrical Engineering University of Vermont Burlington VT USA Dept. of Comput. Sci. & Electr. Eng. Vermont Univ. Burlington VT USA

The capabilities of the Software Development System (SDS) are extended by integrating it with a front end that permits the parallelization of code written in C for implementation onto multiple digital signal processors (DSPs). The FlowGraph Generator (FG) that automatically transfers user C code into a data/control flowgraph is described. The proposed Hierarchical FlowGraph Generator and the proposed Hierarchical Heuristic Scheduler are also described. The former identifies tasks within hierarchies while the latter extends the capability of the current scheduler, by generating dynamic L-levels that can be used to schedule tasks inside loops and functions. The resulting finer grain parallelism has the potential for higher speedups.< >

关键词： Digital signal processing Flow graphs signal processing signal processing algorithms Digital signal processing chips User interfaces Programming Dynamic scheduling Laboratories computer science

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Metal–oxide–semiconductor characterization of silicon surfaces thermally oxidized after reactive ion etching and magnetically enhanced reactive ion etching

Journal of Vacuum Science & Technology B: Microelectronics a...

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Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures processing, Measurement, and Phenomena 1993年第2期11卷 249-252页

作者： Kenneth T. Settlemyer, Jr. Jerzy Ruzyllo David K. Hwang Herbert J. Leary, Jr. Electronic Materials and Processing Research Laboratory Department of Electrical and Computer Engineering The Pennsylvania State University University Park Pennsylvania 16802 IBM General Technology Division East Fishkill Facility Hopewell Junction New York 12533

In this study the performance of reactive ion etching (RIE) and magnetically enhanced reactive ion etching (MERIE) processes in pregate oxidation etching of the field oxide are compared. The comparison is carried out through metal–oxide–semiconductor (MOS) characterization of oxides and interfaces formed on etched silicon surfaces. The results revealed differences in the outcome of RIE and MERIE processes with the latter displaying overall superior characteristics. MERIE induced surface damage is shallower, and is mostly removed during oxide growth. RIE damage propagates deeper into the Si bulk and still influences the MOS devices even after the top Si layers are converted into the oxide. The results obtained emphasize the importance of adequate cleaning of silicon surfaces following RIE/MERIE processes.

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A Framework for Compile-Time Selection of Parallel Modes in an Simd/spmd Heterogeneous Environment

A Framework for Compile-Time Selection of Parallel Modes in ...

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Workshop on Heterogeneous processing

作者： D.W. Watson H.J. Siegel J.K. Antonio M.A. Nichols M.J. Atallah Parallel Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA NCR Corporation San Diego CA USA Computer Sciences Department Purdue University West Lafayette IN USA

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Teacon--a simulator for computer-aided teaching of process control

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computer Applications in engineering Education 1993年第4期1卷 307-307页

作者： Feyo, de Azevedo, S. Oliveira, F. Cardoso, A.C. Departamento de Engenharia Química Faculdade de Engenharia Universidade do Porto Rua dos Bragas 4099 Porto Codex Portugal Sebastião Feyo de Azevedo:is an Associate Professor of Chemical Engineering at the University of Porto. He is a licenciate in chemical engineering from the University of Porto (1973) and earned his PhD in Chemical Engineering from the University of Wales (1982). His interests are in the areas of modeling optimization and process control. Departamento de Electrónica Industrial Universidade do Minho Largo do Paço 4700 Braga Portugal Filomena Oliveira:is a graduate of the Chemical Engineering Department University of Porto 1986. She earned an MSc degree in Electrical Engineering from the same University (1991). She is currently Assistant-Lecturer in the Department of Industial Electronics University of Minho and is working toward her PhD in the control of biological reactors. Departamento de Engenharia Electrotécnica e dos Computadores Faculdade de Engenharia Universidade do Porto Rua dos Bragas 4099 Porto Codex Portugal Artur Capelo Cardoso:is a Lecturer at the Department of Electrical and Computer Engineering of the University of Porto. He earned his PhD from Syracuse University in 1987. His interests are in the areas of electronics signal processing and control.

“TEACON—TEAching CONtrol” is a PC-based package for computer-aided teaching of digital control of Single Input-Single Output (SISO) systems. A large variety of processes and control actions is possible. The program simulates systems in “real time” or faster than “real time.” Process and control parameters can be changed on-line during runs. Set-point and process load can also vary according to predefined functions. The program computes the ISE, IAE, and ITAE indexes, allowing studies of controller tuning and performance. Other characteristics which enhance the simulation of real systems are the saturation of sensors and controller at 0 and 100%, the ability to superimpose noises on the measurements, and the possibility of defining dead-times associated with the measurements and with the process.

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Measurements of power and current components in unbalanced and distorted three‐phase systems

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European Transactions on electrical Power 1993年第1期3卷 75-83页

作者： Andria, G. Salvatore, L. Savino, M. Trotta, A. Dr. Gregorio Andria (1956) AEI received the M. S. degree in Electrical Engineering from the State University of Bari/Italy in 1981 and the Ph. D. degree in Electrical Engineering in 1987 from the same University. From 1981 to 1983 he was working in the Electrotechnics and Electronics Department of the University of Bari as a member of the research team on electrical measurements. From 1984 to 1986 he was a Doctoral Fellow and currently he is a researcher in the same department. His research interests are in the fields of electrical and electronic measurements on components and systems including digital measurements for the analysis of electrical quantities in non-sinusoidal systems and the design of integrated optical sensors for measurement and control of non-electrical physical quantities. (Department of Electrotechnics and Electronics Faculty of Engineering polytechnic of Bovia E. Orabona 4 1-70125 Bari. Italy T +3980/242266 Fax + 3980/242410) Prof. Luigi Salvatore (1945) AEI received the degree in electrical engineering from the University of Bari/Italy in 1970. Since 1976 he has worked in the Electrotechnical and Electronic Department of the same University as a member of the research team on electrical machines. From 1983 to 1987 he was a researcher of electrical machines in the same department. Since 1987 he has been an Associate Professor of electrical machines at the University of Bari. At the present time his research interests include the control monitoring and diagnostics of AC drives and the areas of signal processing anddigital measurements on power electronics systems. (Department of Electrotechnics and Electronics Faculty of Engineering Polytechnic of Bari via E. Orabona 4 I-70125 Bari Italy T + 3980/242258 Fax + 3980/242410) Prof. Mario Savino (1947) AEI received the degree in Electrical Engineering from the University of Barif Italy in 1971. Since then he has been working in the Electrotechnical Institute of Bari until 1973 as researcher from 1973 to 1982 as Assistant Profe

The paper deals with the instantaneous power theory in three‐phase circuits by using the instantaneous time phasors of voltage and current. Particularly it is shown that the instantaneous components of the current time‐phasor in a rotating reference frame p‐q, oriented in such a way that the instantaneous voltage time‐phasor points to the p‐axis direction, represent the active and reactive currents. These components give rise to instantaneous real and imaginary powers, respectively. The spectral analysis of the above‐mentioned time‐phasors gives the harmonic symmetrical components of positive and negative sequence of voltage and current three‐phase systems. The line‐by‐line product of the voltage sequence spectrum by the complex conjugate of the current sequence spectrum gives the DC components of the instantaneous real and imaginary powers. The paper shows also that the instantaneous active and reactive currents are different from those defined on grounds of the Fryze's theory, which can be determined from the voltage and current sequence spectra. Copyright © 1993 John Wiley & Sons, Ltd.

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ON THE COMPUTATION OF RUNNING DISCRETE COSINE AND SINE TRANSFORMS

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IEEE TRANSACTIONS ON signal processing 1992年第6期40卷 1430-1437页

作者： MURTHY, NR SWAMY, MNS Centre for Signal Processing and Communications Department of Electrical and Computer Engineering Concordia University Montreal Canada

There exist some situations in signal processing where it is necessary to compute in real time, the transform coefficients of a set of N time domain samples in a block that gets updated continuously with the arrival of a new sample. A familiar example is the frequency domain implementation of a tapped delay line (TDL) adaptive filter. One method of computing the updated (running or instantaneous) transform coefficients without resorting to the computation of N point transform each time the block gets updated, is to use the shift property of the transform. For the computation of the updated discrete cosine transform-II (DCT-II), discrete sine transform-II (DST-II), discrete cosine transform-IV (DCT-IV), and discrete sine transform-IV (DST-IV) as defined in [5], usage of the shift property requires simultaneous computation (if not available as a by-product of the desired transform computation process) and updating of corresponding DST-II, DCT-II, DST-IV, and DCT-IV, respectively. This requirement of an additional transform computation and (or) updating, results in an increased computational burden. In this paper, we give an alternate algorithm for computing updated transform coefficients for DCT-II, DST-II, DCT-IV, and DST-IV that is computationally attractive for real-time implementation. An architecture for the VLSI implementation of the proposed algorithms is also given.

关键词： Discrete transforms Adaptive filters signal processing algorithms Least squares approximation Adaptive signal processing Frequency domain analysis Delay lines computer architecture Very large scale integration Councils

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