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Frontiers of Massively Parallel Computation

作者： S.A. Fineberg T.L. Casavant B.H. Pease Computer Science Corporation USA Parallel Processing Laboratory Department of Electrical and Computer Engineering University of Iowa Iowa IA USA

The communication latency problem is presented with special emphasis on RISC (reduced instruction set computer) based multiprocessors. An interprocessor communication model for parallel programs based on locality is presented. This model enables the programmer to manipulate locality at the language level and to take advantage of currently available system hardware to reduce latency. A hardware node architecture for a latency-tolerant RISC-based multiprocessor, called Seamless, that supports this model, is presented. The Seamless architecture includes the addition of a hardware locality manager to each processing element, as well as an integral runtime environment and compiler.< >

关键词： Hardware Delay Yarn Parallel processing Reduced instruction set computing Costs Coprocessors Communication system control Parallel architectures Synchronization

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Optical Properties and Structure of Microcrystalline Silicon

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MRS Online Proceedings Library 1992年第1期258卷 235-240页

作者： Hien V. Nguyen Ilsin An Youming Li C.R. Wronski R.W. Collins Materials Research Laboratory The Pennsylvania State University University Park USA Department of Physics USA Department of Electrical and Computer Engineering and the Center for Electronic Materials and Processing USA

The optical properties of thin film microcrystalline silicon (μc-Si:H) prepared by plasma-enhanced chemical vapor deposition (PECVD) have been studied by real time spectroscopie ellipsometry in the nucleation regime as isolated crystalline particles increase in size. A simple geometric model of nucleation allows us to remove the dominant effect of voids and extract the dielectric functions of the crystallites themselves. We find that the results can be understood in terms of a classical size effect whereby limitations on the electron mean free path by scattering at crystallite surfaces control the absorption onset from 2.0 to 3.0 eV. Finally, we describe how well-ordered, continuous 15 Å c-Si films can be prepared on metal substrates.

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The Upper Bounds for Delay and Cell Loss Probability of ATM Traffic in a Finite Capacity Polling System

The Upper Bounds for Delay and Cell Loss Probability of ATM ...

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Southeastern Symposium on System Theory

作者： A.A. Nilsson Y.F. Jou Fuyung Lai Center for Communications and Signal Processing Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA IBM NC USA

This paper focuses on the upper bounds for both the mean delay and the probability of cell loss that bursty arrivals incur in a finite capacity multiqueue system with nonexhaustive cyclic service. We compute the upper bounds for this system by considering a cell multiplexer with the same arrival processes and equal queue capacity. Under the ATM environment, the mean delay obtained from this multiplexer cannot only serve as an upper bound but also render a fairly accurate estimation for the mean delay of the polling system. For the cell loss probability, we consider a multiple urn model with uniform occupancy distribution which will guarantee the upper bound. A heuristic method is proposed to give better estimates for cases which have medium to high cell loss rate.

关键词： Capacity planning Switches Asynchronous transfer mode Traffic control Upper bound Delay estimation Joining processes Telecommunication traffic Road transportation signal processing

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Optimal nonlinear pattern restoration from noisy binary figures

Optimal nonlinear pattern restoration from noisy binary figu...

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Conference on computer Vision and Pattern Recognition (CVPR)

作者： D. Schonfeld Signal and Image Research Laboratory Department of Electrical Engineering and Computer Science University of Illinois Chicago Chicago IL USA

A mathematical framework for the solution of statistical inference problems on a class of random sets is proposed. It is based on a new definition of expected pattern. The least-mean-difference estimator (restoration filter) is proved, under certain conditions, to be equivalent to the minimization of the measure of size (area) of the set-difference between the original pattern and the expected pattern of the estimated (restored) pattern. Consequently, it is proved that, under certain conditions, if the estimator (restoration filter) is unbiased, then it is the least mean difference estimator (restoration filter).< >

关键词： Noise figure Image restoration Pattern analysis Filters Set theory signal restoration Laboratories Area measurement Size measurement Morphology

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Design recovery for relay ladder logic

Design recovery for relay ladder logic

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IEEE Conference on Control Technology and Applications (CCTA)

作者： A. Falcione B.H. Krogh Department of Electrical and Computer Engineering Laboratory of Automatic Systems and Information Processing Carnegie Mellon University Pittsburgh PA USA

An algorithm for converting relay ladder logic (RLL) programs for programmable logic controllers (PLCs) into sequential function chart (SFC) programs is introduced. Since an SFC (a standardization of Grafcet) better represents the sequential flow of control logic, it is considerably easier to understand and modify SFC programs. Existing RLL programs are converted into SFC programs by recovering the underlying sequential control logic. This conversion of the program representation is referred to as design recovery. A basic design recovery algorithm is presented and applied to a simple RLL program for one stage of a batch chemical process. Several fundamental issues in discrete control logic representation and analysis are also identified as fertile areas for future research.< >

关键词： Relays Logic design Programmable control Logic programming Algorithm design and analysis computer languages Chemical processes Laboratories Information processing Automatic logic units

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PERFORMANCE STUDY OF INGAAS/INALAS/INP MODFETS ON HETEROSTRUCTURES GROWN BY OMVPE AND MBE 4

PERFORMANCE STUDY OF INGAAS/INALAS/INP MODFETS ON HETEROSTRU...

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4TH INTERNATIONAL CONF ON INDIUM PHOSPHIDE AND RELATED MATERIALS

作者： ADESIDA, I TONG, M NUMMILA, K KETTERSON, AA AINA, L MATTINGLY, M Center for Compound Semiconductor Microelectronics Coordinated Science Laboratory Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign 61801 IL United States Allied-Signal Aerospace Company 9140 Old Annapolis Road Columbia 21045 MD United States COMSAT Clarksburg MD United States

ISBN: (纸本)0780305221

Devices fabricated in InAlAs/InGaAs/InP heterostructures have demonstrated superior performance in comparison with GaAs-based heterostructures (1). In particular, InAlAs/InGaAs/InP modulation-doped field effect transistors (MODFETs) with submicron gates have demonstrated higher current drive, higher gain, and better frquency response than their corresponding GaAs-based MODFETs. This advantage is attributed to superior material properties in the form of larger conduction band discontinuity, higher room temperature electron mobility, and higher effective electron velocity. To date, the materials used for realizing these high performance submicron MODFETs have been grown largely by molecular beam epitaxy (MBE). It has recently been shown that excellent InAlAsAnGaAs/InP materials can also be grown using organometallic vapor phase epitaxy (OMVPE) (2). This has led to recent reports of OMVPE-grown InGaAs-channel and InP-channel MODFETs with performances similar to those grown using MBE (3, 4). The flexibility of OMVPE in growing both InP and InGaAs in contrast with conventional MBE makes it more versatile for the realization of materials for optoelectronic integrated circuits (OEICs). In this paper, we present our results on the DC and RF characteristics of OMVPE-grown InAlAs/InGaAs/InP MODFETs (OMVPE MODFETs) as a function of gatelength. These results are compared with results reported in literature for MBE-grown InAlAs/InGaAs/InP MODFETs (MBE MODFETs). © 1992 IEEE.

关键词： Molecular beam epitaxy

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Ultra-Shallow P+/N Junctions Formed by SiF4 Preamorphization and BF3 Implantation Using Plasma Immersion Ion Implantation

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MRS Online Proceedings Library 1992年第1期279卷 255-259页

作者： Erin C. Jones Seongil Im Nathan W. Cheung Plasma Assisted Materials Processing Laboratory Department of Electrical Engineering and Computer Sciences University of California Berkeley USA Department of Materials Science and Mineral Engineering University of California Berkeley USA

Sub-100 nm P+/N junctions are fabricated by implanting wafers in the plasma immersion ion implantation system (PIII). Ions from SiF4 and BF3 plasmas are implanted at energies from 4-6 keV and 2 keV, respectively. The amorphous region formed by SiF4 im-plantion is shown to be effective in slowing B diffusion during a 10 sec, 1060°C rapid thermal anneal step. Channeling and transmission electron microscopy studies show the recrys-tallized amorphous region is comparable in quality to an unprocessed Si wafer, and the implantation and annealing sequence has no detrimental effects on the physical or electrical characteristics of fabricated devices. Diodes have forward ideality factors of 1.05 to 1.06 and reverse leakage as low as 2 nA/cm2 in the diode bulk at -5 V applied bias.

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SELECTIVE WET ETCHING FOR INGAAS/INALAS/INP HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS 4

SELECTIVE WET ETCHING FOR INGAAS/INALAS/INP HETEROSTRUCTURE ...

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4TH INTERNATIONAL CONF ON INDIUM PHOSPHIDE AND RELATED MATERIALS

作者： TONG, M KETTERSON, AA NUMMILA, K ADESIDA, I AINA, L MATTINGLY, M Center for Compound Semiconductor Microelectronics Coordinated Science Laboratory Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign 61801 IL United States Allied-Signal Aerospace Company 9140 Old Annapolis Road Columbia 21045 MD United States COMSAT Clarksburg MD United States

ISBN: (纸本)0780305221

The fabrication procedure of heterostructure field-effect transistors (HFETs) such as modulation-doped field-effect transistors (MODFETs) typically includes two important etching steps. The first is the mesa etch for device isolation, and the second is the gate recess where the cap layer is removed to expose the underlying layer for the Schottky gate formation. The gate recess is also used to achieve the desired drain saturation current. Both etching steps require good etch depth control, although, the control needed for the mesa process is not as critical as that for the gate recess. However, the mesa should not be overetched since metal-gate discontinuity due to breakage can occur at the mesa edge, especially for devices with nanometerdimension gate lengths. It has been shown by Tiwari (1) that excellent etch depth control is imperative in the gate recess process for short-gate-length MODFETs in order to achieve uniform threshold voltages which in turn is essential to the realization of high performance integrated circuits. Therefore, a good selectivity in the etching of the cap layer with respect to the underlying high band-gap layer is required in the fabrication of HFETs. © 1992 IEEE.

关键词： Drain current

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Identifiability of a quadratic equations with unknown coefficients

Identifiability of a quadratic equations with unknown coeffi...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： L. Tong S. Yu R. Liu Department of Electrical and Computer Engineering West Virginia University Morgantown WV USA Laboratory for Image and Signal Analysis Department of Electrical Engineering University of Notre Dame Notre Dame IN USA

A set of simultaneous quadratic equations with unknown coefficients is considered. The motivation for studying the equations is presented. Indeterminacy and identifiability are considered. A main lemma and three theor... 详细信息

关键词： Equations Bismuth Laboratories Image analysis signal analysis Array signal processing Blind equalizers Additive noise Statistics

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Recursive-in-order least squares parameter estimation for 2D Gaussian Markov random field model

Recursive-in-order least squares parameter estimation for 2D...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： C.R. Zou Z.Y. He E.I. Plotkin M.N.S. Swamy Center for Signal Processing and Communications Concordia University Montreal QUE Canada Division of Digital Signal Processing South-East University Nanjing China Department of Radio Engineering South-East University Nanjing China Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada

Presents two recursive-in-order least squares algorithms for parameter estimation of 2D Gaussian Markov random field (GMRF) models. Algorithm I implements the recursive computation by introducing auxiliary variables without changing the structure of the model, while algorithm II realizes the recursive computation by replacing the noncausal symmetric GMRF model by an equivalent causal nonsymmetric model. The concept of recursive path, which is used to increase the speed of computation of the model parameters and accomplish the choice of the optimal model support, is proposed. The computational complexity of both algorithms is O(M/sup 2/m) multiplications per order, where m is the total number of parameters and M/sup 2/ is the size of a sample image.< >

关键词： Least squares approximation Parameter estimation Markov random fields signal processing algorithms Finite impulse response filter Maximum likelihood estimation Filtering algorithms Radio frequency Image edge detection Image segmentation

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