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检索条件"机构=Signal Processing and Control ICs Microelectronics Design Center"
3 条 记 录,以下是1-10 订阅
A reverse converter for the 4-moduli superset {2/sup n/-1, 2/sup n/, 2/sup n/+1, 2/sup n+1/+1}
A reverse converter for the 4-moduli superset {2/sup n/-1, 2...
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Computer Arithmetic (ARITH)
作者: M. Bhardwaj T. Srikanthan C.T. Clarke Signal Processing and Control ICs Microelectronics Design Center Siemens Microelectronics Inc. Singapore Center for High Performance Embedded Systems (CHiPES) Nanyang Technological University Singapore Submetrics Limited Bath UK
The authors propose an extension to the popular {2/sup n/-1, 2/sup n/, 2/sup n/+1} moduli set by adding a fourth modulus "2/sup n+1/+1. This extension leads to higher parallelism while keeping the forward convers... 详细信息
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VLSI costs of arithmetic parallelism: a residue reverse conversion perspective
VLSI costs of arithmetic parallelism: a residue reverse conv...
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Computer Arithmetic (ARITH)
作者: M. Bhardwaj T. Srikanthan C.T. Clark Signal Processing and Control ICs Microelectronics Design Center Siemens Microelectronics (Asia Pacific) Private Limited Singapore Singapore Center for High Performance Embedded Systems (CHiPES) Nanyang Technological University Singapore Singapore
This paper reports how VLSI cost metrics (area, delay, power) of residue reverse converters scale with the cardinality and dynamic range of moduli sets. The study uses CMAC reverse converters, reported previously by t... 详细信息
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The Renaissance-a residue number system based vector co-processor for DSP dominated embedded ASics
The Renaissance-a residue number system based vector co-proc...
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Asilomar Conference on signals, Systems & Computers
作者: M. Bhardwaj B. Ljusanin Signal Processing ICS Microelectronics Design Center Siemens Microelectronics (Asia Pacific) Private Limited Singapore Fachbereich Mikrosystemtechnik Fachhochschule Furtwangen Furtwangen Germany
This paper reports our ongoing investigation of a new paradigm to realize high performance DSP architectures suitable for embedded ASics. The reasons for the significant gap between achievable MAC bandwidth and that d... 详细信息
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