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Estimation of missing data in remote sensing images using t-SVD based tensor completion

Estimation of missing data in remote sensing images using t-...

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2020 International Conference for Emerging Technology, INCET 2020

作者： Srindhuna, M. Baburaj, M. Govt: College of Engineering Signal Processing and Embedded Systems Kannur India

ISBN: (纸本)9781728162218

This paper focuses on estimating the lost information from hyperspectral remote sensing images affected by missing samples. During acquisition or transmission remote sensing images may suffer from missing information. When it is affected by missing information, it cannot be used for further applications such as object detection and classification. Therefore the need to predict the missing data in existing remote sensing images becomes a necessity. The performance of the existing tensor completion techniques are poor when data is missing in all bands of a hyperspectral remote sensing image because they do not adequately utilise the spectral information in all bands. This paper proposes a new technique to overcome these problems by using Tensor Singular Value Decomposition (t-SVD) based Tensor Completion (TC). The spectral as well as spatial information in all bands of a hyperspectral remote sensing image could be utilized to detect all missing data, wherefore existing tensor completion techniques are a failure. The proposed method have been experimentally proved to outperform the existing methods when data is missing in either all of the bands or some of the bands. © 2020 IEEE.

关键词： Object detection

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A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection

A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hard...

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Euromicro Symposium on Digital System Design

作者： Viktor Herrmann Justin Knapheide Fritjof Steinert Benno Stabernack Fraunhofer Institute for Telecommunications Heinrich Hertz Institute Berlin Germany University of Potsdam Embedded Systems Architectures for Signal Processing Potsdam Germany

ISBN: (数字)9781665474047

ISBN: (纸本)9781665474054

With the recent advances in the fields of machine learning, neural networks and deep-learning algorithms have become a prevalent subject of computer vision. Especially for tasks like object classification and detection Convolutional Neu-ronal Networks (CNNs) have surpassed the previous traditional approaches. In addition to these applications, CNNs can recently also be found in other applications. For example the parametrization of video encoding algorithms as used in our example is quite a new application domain. Especially CNN's high recognition rate makes them particularly suitable for finding Regions of Interest (ROIs) in video sequences, which can be used for adapting the data rate of the compressed video stream accordingly. On the downside, these CNN require an immense amount of processing power and memory bandwidth. Object detection networks such as You Only Look Once (YOLO) try to balance processing speed and accuracy but still rely on power-hungry GPUs to meet real-time requirements. Specialized hardware like Field Programmable Gate Array (FPGA) implementations proved to strongly reduce this problem while still providing sufficient computational power. In this paper we propose a flexible architecture for object detection hardware acceleration based on the YOLO v3-tiny model. The reconfigurable accelerator comprises a high throughput convolution engine, custom blocks for all additional CNN operations and a programmable control unit to manage on-chip execution. The model can be deployed without significant changes based on 32-bit floating point values and without further methods that would reduce the model accuracy. Experimental results show a high capability of the design to accelerate the object detection task with a processing time of 27.5 ms per frame. It is thus real-time-capable for 30 FPS applications at frequency of 200 MHz.

关键词： Computational modeling Video sequences Object detection Throughput Real-time systems Classification algorithms Convolutional neural networks

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Exploration of Optimizing FPGA-based Qubit Controller for Experiments on Superconducting Quantum Computing Hardware

Exploration of Optimizing FPGA-based Qubit Controller for Ex...

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IEEE International Conference on Electro-Information Technology

作者： Hans Johnson Silvia Zorzetti Jafar Saniie Department of Electrical and Computer Engineering Embedded Computing and Signal Processing (ECASP) Research Laboratory Illinois Institute of Technology Chicago IL U.S.A. Superconducting Quantum Materials and Systems Center (SQMS) Fermi National Accelerator Laboratory Batavia IL U.S.A.

This work explores avenues and target areas for optimizing FPGA-based control hardware for experiments conducted on superconducting quantum computing systems and serves as an introduction to some of the current research at the intersection of classical and quantum computing hardware. With the promise of building larger-scale error-corrected quantum computers based on superconducting qubit architecture, innovations to room-temperature control electronics are needed to bring these quantum realizations to fruition. The QICK (Quantum Instrumentation Control Kit) is one leading experimental FPGA-based implementations. However, its integration into other experimental quantum computing architectures, especially those using superconducting radiofrequency (SRF) cavities, is largely unexplored. We identify some key target areas for optimizing control electronics for superconducting qubit architectures and provide some preliminary results to the resolution of a control pulse waveform. With optimizations targeted at 3D superconducting qubit setups, we hope to bring to light some of the requirements in classical computational methodologies to bring out the full potential of this quantum computing architecture, and to convey the excitement of progress in this research.

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Improving signal-to-Noise Ratio (SNR) for Readout signals Using Adaptive Filters on Reconfigurable Controls Hardware

Improving Signal-to-Noise Ratio (SNR) for Readout Signals Us...

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Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Hans Johnson Silvia Zorzetti Jafar Saniie Department of Electrical and Computer Engineering Embedded Computing and Signal Processing (ECASP) Research Laboratory Illinois Institute of Technology Chicago IL U.S.A. Fermi National Accelerator Laboratory Superconducting Quantum Materials and Systems Center (SQMS) Batavia IL U.S.A.

This study investigates the optimization of signal-to-Noise Ratio (SNR) in superconducting quantum computing readout signals through adaptive filtering. Quantum computing technology has the potential to revolutionize various fields by delivering exponential speedup in solving certain computational problems. However, the technology's practical implementation is hindered by the difficulty of extracting clean, reliable signals during the readout phase, with various sources of noise presenting a significant barrier to clean signals. This noise, often present in readout profiles due to imperfect isolation, degrades the system's overall SNR, thus impeding the ability to extract the quantum state accurately. The research leverages the power of adaptive filtering to improve the SNR of quantum computing readout signals. Specifically, an adaptive filter is implemented in a PYNQ overlay on an FPGA, and eventually will be connected to a quantum computing system. The system models the noise with a Least Mean Squares (LMS) adaptive filter, and then subtracts the estimated noise from the received signal to improve the SNR. A Direct Memory Access (DMA) channel is used to handle the signal processing, delivering efficient, high-speed data transfer between the PYNQ system and the hardware. The study explores the benefits of this adaptive filtering technique, potentially providing a significant contribution to practical and fast quantum computing.

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Demonstrating the Potential of Adaptive LMS Filtering on FPGA-Based Qubit Control Platforms for Improved Qubit Readout in 2D and 3D Quantum processing Units

Demonstrating the Potential of Adaptive LMS Filtering on FPG...

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Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Hans Johnson Nicholas Bornman Taeyoon Kim David Van Zanten Silvia Zorzetti Jafar Saniie Department of Electrical and Computer Engineering Embedded Computing and Signal Processing (ECASP) Research Laboratory Illinois Institute of Technology Chicago IL U.S.A. Fermi National Accelerator Laboratory Superconducting Quantum Materials and Systems (SQMS) Center Batavia IL U.S.A. Department of Physics and Astronomy Center for Applied Physics and Superconducting Technologies (CAPST) Northwestern University Evanston IL U.S.A.

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

Advancements in quantum computing underscore the critical need for sophisticated qubit readout techniques to accurately discern quantum states. This abstract presents our research intended for optimizing readout pulse fidelity for 2D and 3D Quantum processing Units (QPUs), the latter coupled with Superconducting Radio Frequency (SRF) cavities. Focusing specifically on the application of the Least Mean Squares (LMS) adaptive filtering algorithm, we explore its integration into the FPGA-based control systems to enhance the accuracy and efficiency of qubit state detection by improving signal-to-Noise Ratio (SNR). Implementing the LMS algorithm on the Zynq UltraScale+ RFSoC Gen 3 devices (RFSoC 4x2 FPGA and ZCU216 FPGA) using the Quantum Instrumentation Control Kit (QICK) open-source platform, we aim to dynamically test and adjust the filtering parameters in real-time to characterize and adapt to the noise profile presented in quantum computing readout signals. Our preliminary results demonstrate the LMS filter's capability to maintain high readout accuracy while efficiently managing FPGA resources. These findings are expected to contribute to developing more reliable and scalable quantum computing architectures, highlighting the pivotal role of adaptive signal processing in quantum technology advancements.

关键词： Three-dimensional displays Accuracy Filtering Qubit signal processing algorithms Superconducting filters Real-time systems Reliability Field programmable gate arrays signal to noise ratio

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Estimation of Missing Data in Remote Sensing Images Using t-SVD based tensor completion

Estimation of Missing Data in Remote Sensing Images Using t-...

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Emerging Technology (INCET), International Conference for

作者： M. Srindhuna M. Baburaj Govt: College of Engineering Signal Processing and Embedded Systems Kannur India Govt: Engineering College Kozhikkode Kozhikkode India

ISBN: (数字)9781728162218

ISBN: (纸本)9781728162225

关键词： Tensile stress Hyperspectral imaging Singular value decomposition Estimation Image reconstruction

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A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution

A High Throughput MobileNetV2 FPGA Implementation Based on a...

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International Conference on Field Programmable Logic and Applications

作者： Justin Knapheide Benno Stabernack Maximilian Kuhnke Fraunhofer Institute for Telecommunications Heinrich Hertz Institute Berlin Germany University of Potsdam Embedded Systems Architectures for Signal Processing Potsdam Germany

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Convolutional Neural Networks are widely applied to various computer vision tasks. For most of these applications, high throughput and energy efficiency are top priorities. MobileNetV2 features very low memory requirements as well as a relatively small model size. On the ILSVRC 2012 classification challenge, it provides a decent prediction accuracy of 71.7 percent at low computational requirements. We present an FPGA based MobileNetV2 accelerator with a high throughput of 1050 frames per second at a power consumption of 34 watt under full load. This equates to a power efficiency of 32 milli-joule per frame. We describe our approach of using stream interfaces and auto-generated control signals to enable fast design of flexible architectures. By using quantization techniques, limiting the accuracy of the used number format to a 16 bit fixed point format, we were able to reduce the memory usage for weights as well as activations by a factor of two. Since the basic building block of MobileNetV2 can be used to build higher performance networks as well, the findings of this paper remain applicable, when higher prediction accuracies are required.

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Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers

Hardware and Software Components towards the Integration of ...

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Euromicro Symposium on Digital System Design

作者： Fritjof Steinert Niklas Schelten Anton Schulte Benno Stabernack Fraunhofer Institute for Telecommunications Heinrich Hertz Institute Berlin Germany Embedded Systems Architectures for Signal Processing University of Potsdam Potsdam Germany

ISBN: (数字)9781728195353

ISBN: (纸本)9781728195360

The usage of Field Programmable Gate Arrays(FPGAs) as application-specific accelerators in data centers has grown rapidly in recent years. The main reasons for this are the higher throughput of application-specific accelerators, an improved latency behavior as well as higher energy efficiency compared to conventional computing systems with CPUs and GPUs. In particular, network-attached FPGA accelerators exhibit excellent latency behavior and very high energy efficiency. The high efficiency not only decreases operating costs, but also results in a lower carbon footprint. A disadvantage compared to conventional CPUs and GPUs is the difficult programmability as well as the integration into data centers, which hinders a widespread adoption. To simplify the integration of FPGA accelerators in heterogeneous data centers, we have designed a flexible hardware and software framework to overcome these problems. We also show which components are necessary to fulfill the requirements within a data center.

关键词： Field programmable gate arrays Data centers Hardware Sockets Random access memory Virtualization Software

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A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators

A High-Throughput, Resource-Efficient Implementation of the ...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Niklas Schelten Fritjof Steinert Anton Schulte Benno Stabernack Fraunhofer Institute for Telecommunications Heinrich Hertz Institute Berlin Germany University of Potsdam Embedded Systems Architectures for Signal Processing Potsdam Germany

The integration and usage of application specific processor cores and accelerators into data center installations is state of the art since at least one decade with the advent of GPGPUs. In most cases these accelerators are coupled via standard PCIe interfaces to the corresponding host computers, which leads to disadvantages in interoperability, scalability and overall power consumption. As a viable alternative to PCIe-attached FPGA accelerators this paper proposes standalone FPGAs as network-attached accelerators (NAA). To provide all necessary infrastructure for decoupled FPGAs we present a framework incorporating a network stack which implements RDMA over Converged Ethernet v2 (RoCEv2) by Infiniband and UDP/IP communication for high-speed and low-latency data transfer. We present the requirements such a framework has to fulfill and how this can be satisfied with our network stack. For NAAs to be used instead of PCIe coupled FPGAs the framework needs to use as little resources as possible and at the same time provide similar throughput and latency. Therefore, we show that our network stack is capable of 100 Gb/s throughput with latencies of less than 4 μs while using less than 10% of the available resources on a mid-range FPGA. Based on our results, network-attached FPGAs are a great alternative to the more energy intensive PCIe-attached FPGA accelerators.

关键词： Data centers Protocols Power demand Scalability Ethernet Throughput Hardware

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Performance Comparison of FFT, DCT, DWT and DDDWT-OFDM in Rayleigh Channel 2

Performance Comparison of FFT, DCT, DWT and DDDWT-OFDM in Ra...

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2nd International Conference on Smart systems and Inventive Technology, ICSSIT 2019

作者： Leela Rani, D. Bharathi, M. Padmaja, N. Centre of Communication and Signal Processing SVEC Department of ECE Tirupati517102 India Centre of VLSI and Embedded Systems SVEC Department of ECE Tirupati517102 India

ISBN: (纸本)9781728121192

Cost effective, easily accessible and high speed wireless communication systems are of great demand. Hence implementation of efficient methods to improve spectral efficiency and Bit Error Rate (BER) performance in multicarrier systems has become an important issue. Conventional Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier technique to increase data rates of wireless communication channel. Implementation of conventional OFDM system involves Inverse Fast Fourier Transform (IFFT) and Fast Fourier Transform (FFT) at Transmitter and Receiver. Besides numerous advantages with these systems, Cyclic Prefix has to be appended to minimize Inter Symbol Interference (ISI) and increase Spectral efficiency. Wavelet based system on the other hand avoids cyclic prefix requirement, provides side lobes which are very narrow, improves spectral efficiency and better BER performance. The performance of conventional multicarrier FFT-OFDM can be improved by the application of Wavelet Transforms like Discrete Wavelet Transform (DWT), Double Density Discrete Wavelet Transforms (DDDWT). The performance is compared in terms of BER verses SNR using Discrete Cosine Transform (DCT), DWT and DDDWT. The complex wavelet transforms based OFDM performed better than conventional multicarrier FFT-OFDM. © 2019 IEEE.

关键词： Discrete wavelet transforms

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