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Optical Memory Elements Based on Hetero-nipi Superlattice Asymmetric Cavity Spatial Light Modulators

Optical Memory Elements Based on Hetero-nipi Superlattice As...

引用

Spatial Light Modulators and Applications, SLM 1993

作者： Hibbs-Brenner, M.K. Mukherjee, S.D. Lehman, J. Ruden, P.P. Liu, J.J. Sawchuk, A.A. Hsu, W.-F. Honeywell Systems and Research Center 10701 Lyndale Avenue South BloomingtonMN55420 United States Dept. of Electrical Engineering and Computer Science University of Minnesota MinneapolisMN55455 United States Signal and Image Processing Institute University of Southern California Los AngelesCA90089-2564 United States

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Reliability assessment of self-timed VLSI circuits

Reliability assessment of self-timed VLSI circuits

引用

Custom Integrated Circuits Conference (CICC)

作者： Chen-Hao Chang B.J. Sheu S.M. Gowda Department of Electrical Engineering Electrophysics and Systems Signal and Image Processing Institute University of Southern California Los Angeles CA USA University of Southern California Los Angeles CA US T.J. Watson Research Center IBM Corporation Yorktown Heights NY USA

Self-timed VLSI circuits can avoid problems of clock distribution and achieve 500 MHz or higher-speed data processing. The RELY circuit reliability simulator is used to investigate the comparative reliability of two-phase, single-phase, and self-timed circuits. Reliability simulation techniques and analysis results on submicron CMOS circuits are presented.

关键词： Very large scale integration Circuit simulation Clocks Degradation Integrated circuit reliability Substrates MOSFETs Monitoring Analytical models CMOS technology

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An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing

引用

1992 IEEE International Conference on Systems engineering

作者： Okada, Hiroto Sheu, Bing J. Chang, Chia-Fen Signal and Image Processing Institute Center for Neural Engineering University of Southern California Los AngelesCA90089-0271 United States

ISBN: (纸本)0780307348

This paper describes a mixed-signal VLSI design for early vision processing, which includes an analog edge detection chip with embedded array photosensors and a digital multi-processor chip. The system architecture overview shows the combination of the analog chip and the digital processors can perform high efficient processing in the neural-based vision processing. The analog edge detection chip consisting of 258 × 258 photosensor cells can be implemented in an area of 13.5 × 15.5 mm2 using the new MOSIS 0.8 μm CMOS technology. The digital multi-processor chip which includes sixty four processing elements can be implemented in a 15.0 × 18.0 mm2 chip using a industrial-scale 0.5 μm CMOS technology from TRW, Inc. A system implementation for fingerprint verification is presented as an example of possible applications. © 1992 IEEE.

关键词： Edge detection

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Digital VLSI Multiprocessor Design for Neurocomputers

Digital VLSI Multiprocessor Design for Neurocomputers

引用

1992 International Joint Conference on neural Networks, IJCNN 1992

作者： Chang, Chia-Fen Sheu, Bing J. Department of Electrical Engineering Center for Neural Engineering the Signal and Image Processing Institute University of Southern California Los AngelesCA90089-0271 United States

ISBN: (纸本)0780305590

The architecture and circuit design of digital processors for general-purpose neurocomputing are presented. The processing element is suitable for a tightly coupled multiprocessor chip connected in 1-dimensional ring or 2-dimensional mesh fashion. An off-chip microprogrammed array controller broadcasts instructions to all processing elements. Mappings of the feedforward and feedback operations in the back-propagation neural network into the mesh-connected processing element matrix are described. Detailed design of the circuit blocks is also described. More than 128 processing elements can be implemented in a super chip through the advanced 0.5-μm CMOS technology from TRW Inc. to achieve 2.56 billion operations per second. The multiprocessor chip can be used for various types of neural networks including back-propagation multilayer networks and self-organizing networks. © 1992 IEEE

关键词： Backpropagation

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Digital VLSI multiprocessor design for neurocomputers

Digital VLSI multiprocessor design for neurocomputers

引用

International Joint Conference on neural Networks (IJCNN)

作者： C.-F. Chang B.J. Sheu Department of Electrical Engineering Center for Neural Engineering the Signal and Image Processing Institute University of Southern California Los Angeles CA USA

The architecture and circuit design of digital processors for general-purpose neurocomputing are presented. The processing element is suitable for a tightly coupled multiprocessor chip connected in one-dimensional ring or two-dimensional mesh fashion. An off-chip microprogrammed array controller broadcasts instructions to all processing elements. Mappings of the feedforward and feedback operations in the backpropagation neural network into the mesh-connected processing element matrix are described. Detailed design of the circuit blocks is also described. More than 128 processing elements can be implemented in a super chip by use of advanced 0.5- mu m CMOS technology to achieve 2.56 billion operations per second.< >

关键词： Very large scale integration neural networks image processing Neurons CMOS technology Computer architecture neural engineering signal processing Circuit synthesis Coupling circuits

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An Electronic Neuroprocessor for image Motion Detection

An Electronic Neuroprocessor for Image Motion Detection

引用

IJCNN International Joint Conference on neural Networks

作者： Ji Chien Lee Hiroto Okada Bing J.Sheu Rama Chellappa Department of Electrical Engineering Signal and Image Processing Institute and Center for Neural Engineering University of Southern California Los Angeles CA 90089-0271

A VLSI design of a competitive neural network for video motion detection,using mixed-signal mode approach,is *** detection is performed massively and parallelly by a two-dimensional multiprocessor array which is consisted of an analog *** the array,local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme,while global data communication between a host computer and the neuroprocessors is achieved in a digital common *** results of the analog circuit blocks and system-level analysis are also presented.A 1.0×1.9-cm chip in a 0.8-μm CMOS technology can accommodate 64 velocity-selective *** chip can achieve 104 Giga connections per second.

关键词： image frame An Electronic Neuroprocessor for image Motion Detection

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An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing

An analog VLSI edge detection chip and digital multiprocesso...

引用

IEEE International Conference on Systems engineering

作者： H. Okada B.J. Sheu C.-F. Chang Department of Electrical Engineering (Electrophysics and Systems) Signal & Image Processing Institute Center for Neural Engineering University of Southern California CA USA Dept. of Electr. Eng. Univ. of Southern California Los Angeles CA USA

A mixed-signal VLSI design for early vision processing, which includes an analog edge detection chip with embedded array photosensors and a digital multiprocessor chip, is described. The system architecture overview shows that the combination of the analog chip and the digital processors can perform highly efficient processing in neural-based vision processing. The analog edge detection chip consisting of 258*258 photosensor cells can be implemented in an area of 13.5 mm*15.5 mm using the MOSIS 0.8- mu m CMOS technology. The digital multiprocessor chip, which includes 64 processing elements, can be implemented in a 15.0-mm*18.0-mm chip using an industrial-scale 0.5- mu m CMOS technology. A system implementation for fingerprint verification is presented as an example of possible applications.< >

关键词： Very large scale integration image edge detection Circuits CMOS technology image processing Random access memory Control systems neural networks image sensors Voltage

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A computational vision approach to image registration

A computational vision approach to image registration

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International Conference on Pattern Recognition

作者： Q. Zheng R. Chellappa Signal and Image Processing Institute University of Southern California Los Angeles CA USA Department of Electrical Engineering Center for Automation Research University of Maryland College Park MD USA

Automatic image registration is important for many multiframe-based image analysis applications. In this paper, a computational vision approach is presented for the estimation of 2-D translation, rotation, and scale from two partially overlapping images. The approach has the following features: (1) an illuminant direction estimator is used to obtain an initial estimate of camera rotation; (2) feature points are located based on a Gabor wavelet model for detecting local curvature discontinuities; (3) estimation of rotation and translation is formulated as a linear problem; and (4) hierarchical coarse-to-fine matching is used. This results in a fast and novel algorithm that produces good results even when large rotations and scale changes have occurred between the two frames and the images are devoid of significant features. Several applications of the algorithm are presented.< >

关键词： Computer vision image registration Cameras Motion estimation Object detection image motion analysis Robustness Feature extraction Forward contracts Coordinate measuring machines

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Analog VLSI neural network implementations of hardware annealing and winner-take-all functions 34

Analog VLSI neural network implementations of hardware annea...

引用

34th Midwest Symposium on Circuits and Systems, MWSCAS 1991

作者： Choi, Joongho Sheu, Bing J. Gowda, Sudhir M. Department of Electrical Engineering Signal and Image Processing Institute National Center for Integrated Photonic Technology University of Southern California Los AngelesCA90089-0271 United States

ISBN: (纸本)0780306201

The hardware annealing function plays a key role in searching for the optimal solutions for Hopfield neural networks and multi-layer back-propagation networks. The winner-take-all function is required in the operation of competitive-learning networks. Design and VLSI implementation of these two functions have been accomplished. Demonstration of hardware annealing with different synapse circuits is presented. The new high-speed analog winner-take-all circuit is linearly extendable to at least 1,024 inputs. © 1992 IEEE.

关键词： Hopfield neural networks

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A trainable analog neural chip for image compression

A trainable analog neural chip for image compression

引用

Custom Integrated Circuits Conference (CICC)

作者： C.-F. Chang B.J. Sheu W.-C. Fang J. Choi Department of Electrical Engineering Signal and Image Processing Institute and Center of Neural Engineering University of Southern California Los Angeles CA USA

Video motion estimation and high-ratio image compression are two key data processing steps for advanced television systems and imaging machines. The detailed circuit design of a vector quantization chip with the full-search scheme is presented. Each 5*5 image block with 256 pixel-gray levels can be quantized into the 6-bit codebook by a prototype chip of 4.6 mm*6.8 mm in a 2- mu m scalable MOSIS technology. A speedup factor of 750 over a Sun-3/60 workstation has been obtained. Adaptive codebook learning can be performed with a digital coprocessor.< >

关键词： neural network hardware image coding Video compression Motion estimation Data processing TV Circuit synthesis Vector quantization Pixel Prototypes

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