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A trainable analog neural chip for image compression

A trainable analog neural chip for image compression

引用

Custom Integrated Circuits Conference (CICC)

作者： C.-F. Chang B.J. Sheu W.-C. Fang J. Choi Department of Electrical Engineering Signal and Image Processing Institute and Center of Neural Engineering University of Southern California Los Angeles CA USA

Video motion estimation and high-ratio image compression are two key data processing steps for advanced television systems and imaging machines. The detailed circuit design of a vector quantization chip with the full-search scheme is presented. Each 5*5 image block with 256 pixel-gray levels can be quantized into the 6-bit codebook by a prototype chip of 4.6 mm*6.8 mm in a 2- mu m scalable MOSIS technology. A speedup factor of 750 over a Sun-3/60 workstation has been obtained. Adaptive codebook learning can be performed with a digital coprocessor.< >

关键词： neural network hardware image coding Video compression Motion estimation Data processing TV Circuit synthesis Vector quantization Pixel Prototypes

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Multiprocessor-based video motion detection using adaptive neural systems

Multiprocessor-based video motion detection using adaptive n...

引用

International Symposium on VLSI Technology, Systems and Applications

作者： J.C. Lee B.J. Sheu C.F. Chang R. Chellappa Department of Electrical Engineering Signal and Image Processing Institute and Center of Neural Engineering University of Southern California Los Angeles CA USA

Fast motion detection is an important step in the high-speed video/vision processing systems. System-level design of a 2-dimensional mesh-concerned competitive neural network for video motion detection is presented. The motion information from a sequence of images can be obtained through mixed-analog/digital signal processing. Massively parallel neurocomputing is performed by multiple copies of compact and efficient neuroprocessors. Inter-processor data transfer is carried out by dedicated point-to-point analog interconnections. Global data communication between the host computer and neuroprocessors is through the digital common bus to maintain strong signal strength. An extendable analog winner-take-all circuit is used to implement the competition function with a minimal delay time. A 1.5*2.8-cm/sup 2/ chip in a 1.2- mu m CMOS technology can accommodate 64 velocity-selective neuroprocessors. This chip can achieve 83.2 Giga-connections per second. By using 128 VLSI neural chips, the speed-up factor over the Sun-4/60 SPARC station-1 is estimated to by 54545.< >

关键词： Motion detection CMOS technology Machine vision System-level design neural networks Digital signal processing Integrated circuit interconnections Data communication Delay effects Very large scale integration

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Hardware annealing for fast retrieval of optimal solutions in Hopfield neural networks

Hardware annealing for fast retrieval of optimal solutions i...

引用

International Joint Conference on neural Networks (IJCNN)

作者： B.J. Sheu B.W. Lee C.-F. Chang Signal and Image Processing Institute and Center of Neural Engineering Department of Electrical Engineering University of Southern California Los Angeles CA USA Bucheon Research and Development Center Samsung Electronics Company Limited South Korea

Due to the feedback characteristics of Hopfield networks, the solutions often get stuck at local minima where the objective functions have surrounding barriers. The theory and procedure of hardware annealing, which can retrieve the optimal solution in parallel, have been developed. In hardware annealing, voltage gains of output neurons in asynchronous VLSI neural chips are increased from an initial low value to a final high value in a continuous fashion. Hardware annealing can be applied to pure analog and mixed analog-digital neurocomputing systems. It achieves a speed-up factor of more than 10000 times over simulated annealing on a SUN-3/60 workstation.< >

关键词： neural network hardware Intelligent networks Hopfield neural networks Very large scale integration Neurons Computational modeling Simulated annealing Boltzmann distribution Voltage Analog-digital conversion

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Analog VLSI neural network implementations of hardware annealing and winner-take-all functions

Analog VLSI neural network implementations of hardware annea...

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： J. Choi B.J. Sheu S.M. Gowda Department of Electrical Engineering Signal and Image Processing Institute and National Center for Integrated Photonic Technology University of Southern California Los Angeles CA USA

Hardware annealing and winner-take-all (WTA) functions have been implemented in 2.0- mu m technology. The hardware annealing technique has been demonstrated using a 4*4 synapse network. Measurement results of a new WTA circuit are presented. The WTA circuit uses transistors biased in saturation to achieve high-speed performance. Since the comparison among the inputs is performed on one common signal line, the circuit can be easily extended to a larger dimension with that common signal line connected throughout the entire circuit. The new high-speed analog winner-take-all circuit can be extended linearly to at least 1024 inputs.< >

关键词： Very large scale integration neural networks neural network hardware Neurons Voltage Simulated annealing Circuit simulation Hopfield neural networks Resistors signal processing

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Passive Navigation in a partially known environment

Passive Navigation in a partially known environment

引用

Workshop on Visual Motion

作者： S. Chandrashekhar R. Chellappa Signal and Image Processing Institute Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA Department of Electrical Engineering Center for Automation Research University of Maryland College Park MD USA

The paper presents an integrated solution to the problem of obtaining the kinematics of a moving vehicle and the 3D locations of salient points in the external environment, based on a sequence of monocular images. The structure of a small number of navigational landmarks in the scene is assumed to be known. The parameters of interest are expressed in an inertial, or 'world' coordinate system, external to the moving vehicle, and are estimated recursively using an extended Kalman filter (EKF). The extraction and matching of feature points are done using a gabor wavelet representation, and are interleaved with the recursive estimation. Experimental results on a real image sequence are given.< >

关键词： Navigation Vehicles Layout Recursive estimation image sequences Cameras Kinematics State estimation Carbon capture and storage signal processing

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neural-based analog trainable vector quantizer and digital systolic processors

Neural-based analog trainable vector quantizer and digital s...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： B.J. Sheu C.F. Chang T.H. Chen O.T.C. Chen Department of Electrical Engineering Center of Neutral Engineering and Signal and Image Processing Institute University of Southern California Los Angeles CA USA Dept. of Electr. Eng. Univ. of Southern California Los Angeles CA USA

Architectures and detailed circuit designs of one analog trainable neural chip and one-digital systolic-processor chip are presented. The analog vector quantizer chip performs full search in a massively parallel fashion with an expandable winner-take-all circuitry which can achieve a 10-b resolution. A high compression ratio of 33 is feasible in many image compression applications. Extensive design of a digital systolic-processor chip has been conducted. Circuit blocks, data communication, and microcodes are created to support either the ring-connected or the mesh-connected systolic array for the retrieving and learning phases of the neural network operation. The digital neural chip can also be configured to implement fuzzy logic systems.< >

关键词： Circuits neural network hardware Artificial neural networks image coding Very large scale integration image processing Neurons Computer architecture Prototypes CMOS technology

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VLSI image processor using analog programmable synapses and neurons

VLSI image processor using analog programmable synapses and ...

引用

International Joint Conference on neural Networks (IJCNN)

作者： B.W. Lee J.-C. Lee B.J. Sheu Department of Electrical Engineering Signal and Image Processing Institute and Center for Neural Engineering University of Southern California Los Angeles CA USA

A VLSI neural network with concurrent network retrieving and learning processes is described. Weightings of analog synapse cells are externally programmed and require dynamic refreshing. Gain-adjustable neurons are used to facilitate electronic annealing to efficiently search for an optimal solution. Two prototype chips which operate in a synchronous fashion and an asynchronous fashion, respectively, were fabricated and tested. The 25-neuron chip for image restoration occupies a silicon area of 4.6×6.8 mm 2 in a MOSIS 2-μm CMOS process and achieves 300×speedup compared with a Sun-3/60 workstation. If implemented in industrial-level 1-μm VLSI technologies, a fully connected general-purpose neural chip with 500 neurons can be achieved in a 1-cm 2 silicon area

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A compact and general-purpose neural chip with electrically programmable synapses

A compact and general-purpose neural chip with electrically ...

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Custom Integrated Circuits Conference (CICC)

作者： B.W. Lee B.J. Sheu Department of Electrical Engineering Signal and Image Processing Institute and Center for Neural Engineering University of Southern California Los Angeles CA USA

A neural chip with 64 neurons and 4096 DRAM-like programmable synapses has been designed and fabricated in 29 mm/sup 2/ area using the 2- mu m scalable CMOS process from MOSIS Service. With 0.2-s refresh cycle, 8-b accuracy in synapses can be achieved for image processing. A system simulation result of image restoration using the programmable synapse chip architecture is also presented. An industrial-level 500-neuron chip with the fully connected synapse array can be implemented in 1- mu m CMOS technologies.< >

关键词： neural network hardware Neurons Circuits neural networks Very large scale integration Transconductance Voltage image processing CMOS technology Difference equations

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Parallel digital image restoration using adaptive VLSI neural chips

Parallel digital image restoration using adaptive VLSI neura...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： J.-C. Lee B.J. Sheu Department of Electrical Engineering Signal and Image Processing Institute and National Center for Integrated Photonic Technology University of Southern California Los Angeles CA USA

Real-time digital image restoration using massively parallel Hopfield neural chips is presented. An efficient mixed-signal VLSI design with analog circuitry to perform neural computation and digital circuitry to process multiple-bit pixel information greatly reduces the network size. Analog programmable synapse cells of 8 bit accuracy are dynamically refreshed. The gain-adjustable neurons enable electronic annealing to quickly reach global minimum in energy function. A prototype 25-neuron chip occupies a silicon area of 4.6*6.8 mm/sup 2/ in MOSIS 2- mu m CMOS process has been designed and tested. The speedup factor for each chip is 90 compared to the Sun-3 workstation. An 100-neuron image-restoration chip is achievable in the industrial-level 1- mu m technologies.< >

关键词： Digital images image restoration Very large scale integration neural network hardware Circuits Analog computers Computer networks Neurons Annealing Prototypes

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Real-time computing of optical flow using adaptive VLSI neuroprocessors

Real-time computing of optical flow using adaptive VLSI neur...

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： W.-C. Fang B.J. Sheu J.-C. Lee Department of Electrical Engineering Signal and Image Processing Institute and National Center for Integrated Photonic Technology University of Southern California Los Angeles CA USA

The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2- mu m CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.< >

关键词： Optical computing Adaptive optics image motion analysis Very large scale integration Optical arrays Multi-layer neural network Stochastic processes CMOS technology neural networks Optical fiber networks

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