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A high-speed high-density array-multiplier-accumulator for digital signal processing

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 1996年第2期79卷 86-97页

作者： Minami, T Kasai, R Matsuda, H Kusaba, R Member NTT LSI Laboratories Atsugi Japan 243-01 Graduated in 1980 from the Department of Electrical Engineering Kyushu University where he received his Master's degree in 1982 and joined NTT. Until March 1986 he was engaged in the development of application software for electronic switching systems. He then engaged in research and development of LSIs for image signal processing. At present he is Senior Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of IEEE. Graduated in 1972 from the Department of Electrical Engineering Osaka University where he received his Master's degree in 1974 and his Ph.D. in 1992. He joined NTT in 1974. He is engaged in research and development of analysis of MOS devices and design of ASIC for communication. At present he is Executive Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of IEEE. Graduated in 1987 from the Department of Communications Tohoku University where he received his Master's degree in 1989 and joined NTT. He is engaged in research and development of high-speed design for image processing LSIs. At present he is Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of the Information Processing Society. Graduated in 1985 from the Department of Electrical Engineering Keio University where he received his Master's degree in 1987 and joined NTT. He is engaged in CAD research. At present he is Senior Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of the Information Processing Society and IEEE.

This paper discusses the downsizing and speed improvement of short-word multiplier-accumulators, which are frequently used in digital signal processors. As a first step, the optimal configuration for an array-type carry-save adder is considered where the shortest path in the full-adder is used to propagate the sum signal and the carry signal is sent to the full-adder of the two lower stages by skipping a stage. A configuration of the full-adder suitable for the structure is proposed. The case of eight partial product additions shows that the delay can be reduced by 22 percent compared to a simple array-type carry-save adder. Then the short-word carry look-ahead adder using the pass-transistor logic is considered. It is shown that a single-stage carry look-ahead circuit with a four-bitwise iterative structure exhibits nearly the same delay as a two-stage carry look-ahead circuit. In other words, the former is better suited to downsizing. This paper intends to examine the effectiveness of the foregoing new array-type carry-save adder and the single-stage carry look-ahead circuit using the 0.5-mu m CMOS technology. A 16-bit x 14-bit + 31-bit multiplier-accumulator has been designed and is evaluated for cases where the array-type carry-save adder is used to handle accumulation as well as partial products. The resulting area and delay are 0.77 x 0.78 mm(2) and 6.8 ns, respectively. The effectiveness of the approach used in this paper is evaluated by constructing a multiplier-accumulator, but the method is also useful in constructing a multiplier.

关键词： product-sum operation array multiplier carry-save adder full-adder carry look-ahead adder

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MORPHOLOGICAL REPRESENTATION OF ORDER-STATISTICS FILTERS

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IEEE TRANSACTIONS ON image processing 1995年第6期4卷 838-845页

作者： CHARIFCHEFCHAOUNI, M SCHONFELD, D Signal and Image Research Laboratory Department of Electrical Engineering and Computer Science University of Illinois Chicago IL USA

In this correspondence, we propose a comprehensive theory for the morphological bounds on order-statistics filters (and their repeated iterations). Conditions are derived for morphological openings and closings to serve as bounds (lower and upper, respectively) on order-statistics filters (and their repeated iterations). Under various assumptions, morphological open-closings and close-openings are also shown to serve as (tighter) bounds (lower and upper, respectively) on iterations of order-statistics filters. Simulations of the application of the results presented to image restoration are finally provided.

关键词： image coding Fractals signal processing algorithms Speech processing Decoding Pixel Heuristic algorithms signal processing Application software Digital images

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Texture segmentation using hierarchical wavelet decomposition

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PATTERN RECOGNITION 1995年第12期28卷 1819-1824页

作者： Salari, E Ling, Z Computer Vision and Image Processing Laboratory Department of Electrical Engineering University of Toledo Toledo OH 43606 U.S.A.

This paper presents a texture segmentation algorithm based on a hierarchical wavelet decomposition. Using Daubechies' four-tap filter, an original image is decomposed into three detail images and one approximate image. The decomposition can be recursively applied to the approximate image to generate a lower resolution of the pyramid. The segmentation starts at the lowest resolution using the K-means clustering scheme and textural features obtained from various sub-bands. The result of segmentation is propagated through the pyramid to a higher resolution with continuously improving the segmentation. The lower resolution levels help to build the contour of the segmented texture, while higher levels refine the process, and correct possible errors.

关键词： Texture segmentation Wavelet transform Clustering algorithm Multiresolution segmentation

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ON THE CONVERGENCE AND ROOTS OF ORDER-STATISTICS FILTERS

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IEEE TRANSACTIONS ON signal processing 1995年第8期43卷 1990-1993页

作者： CHARIFCHEFCHAOUNI, M SCHONFELD, D Signal and Image Research Laboratory Department of Electrical Engineering and Computer Science University of Illinois Chicago Chicago IL USA

In this correspondence, we propose a comprehensive theory of the convergence and characterization of roots of order-statistics filters. Conditions for the convergence of iterations of order-statistics filters are prop... 详细信息

关键词： Convergence Filters signal processing image processing Statistics image restoration signal restoration image converters Computational efficiency Filtering theory

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Partially adaptive radar signal processing: The cross-spectral approach 29

Partially adaptive radar signal processing: The cross-spectr...

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29th Asilomar Conference on signals, Systems and computers, ACSSC 1995

作者： Goldstein, J. Scott Kogon, Stephen M. Reed, Irving S. Williams, Douglas B. Holder, E. Jeff USAF Rome Laboratory RL/C3BA 525 Brooks Rd. Grifilss AFBNY13441-4505 United States Statistical Signal and Image Processing Laboratory Department of Electrical Engineering University of Southern California Los AngelesCA90089-2565 United States Digital Signal Processing Laboratory School of Electrical and Computer Engineering Georgia Institute of Technology AtlantaGA30332-0250 United States

ISBN: (纸本)0818673702

This paper is concerned with reducing the rank of the adaptive weight vector in radar array signal processing. The motivation for reducing the rank is that modern space-time processing requires many more weights than can be supported on airborne and spacesegment platforms. The loss incurred in partially adaptive radar processing is that the steady-state Wiener solution of the lower rank weight vector may not perform as well as the full rank solution. Hence, this paper will be concerned with the Wiener solution of partially adaptive radar arrays and compare the performance of principal component techniques with the recently developed crossspectral technique. © 1996 IEEE.

关键词： Array processing

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An efficient algorithm for DTMF decoding using the subband NDFT

An efficient algorithm for DTMF decoding using the subband N...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S. Bagchi S.K. Mitra Department of Electrical and Computer Engineering Signal and Image Processing Laboratory University of California Santa Barbara CA USA

An algorithm based on the subband nonuniform discrete Fourier transform (SB-NDFT) is proposed for decoding dual-tone multi-frequency (DTMF) signals. To decode a DTMF signal, its energy at the eight DTMF frequencies must be determined by evaluating samples of the NDFT at these frequencies. In the proposed SB-NDFT algorithm, these NDFT samples are computed by decomposing the input signal into two subbands. Since DTMF signals occupy the low-frequency part of the telephone bandwidth, the higher subband can be discarded for a fast, approximate computation. A performance comparison between algorithms based on the NDFT, SB-NDFT, DFT, and SB-DFT shows that the SB-NDFT requires the lowest number of computations to attain a specified level of performance.

关键词： Decoding Frequency Discrete Fourier transforms signal processing image processing Laboratories Telephony Bandwidth Communication system signaling Telephone sets

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Reduction of coding artifacts in low-bit-rate video coding

Reduction of coding artifacts in low-bit-rate video coding

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： R.L. Stevenson Laboratory for Image and Signal Processing Department of Electrical Engineering University of Notre Dame Notre Dame IN USA

The compression of digital video data has many applications in the transmission and storage of video sequences. For moderate compression ratios there are many techniques which can provide satisfactory performance. For high compression ratios, however, typical compression techniques produce noticeable artifacts in the reconstructed video. This paper proposes a technique for the post-processing of motion-compensated compressed video data. The technique utilizes a stochastic regularization approach which can be realized using a simple and fast iterative computational algorithm. The approach has been applied to the post-processing of color video sequences and yields good results.

关键词： Video coding image coding Video compression Video sequences signal processing algorithms Degradation image storage image reconstruction Stochastic processes Laboratories

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VLSI implementation of very-high-order FIR filters

VLSI implementation of very-high-order FIR filters

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： M.A. Soderstrand K. Al-Marayati Digital Signal Processing and Communications Laboratory Department of Electrical and Computer Engineering University of California Davis USA

Very-high-order FIR filters required for the new modulation schemes associated with wireless computer networks and cellular telephones can be implemented in VLSI circuitry using low-power CMOS technology and a novel application of Residue Number System (RNS) arithmetic. Through this approach 20-bit equivalent integer arithmetic can be obtained for filters with 8 to 256 taps with only a modest increase in hardware for filters above 8 taps. Simulations indicate that this new technique can increase dramatically the number of taps implemented on a single VLSI chip when compared with an FIR filter generated using FIRGEN.

关键词： Very large scale integration Finite impulse response filter CMOS technology computer networks Cellular networks Telephony Circuits Application software Digital arithmetic Hardware

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Partially adaptive radar signal processing: the cross-spectral approach

Partially adaptive radar signal processing: the cross-spectr...

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Asilomar Conference on signals, Systems & computers

作者： J.S. Goldstein S.M. Kogon I.S. Reed D.B. Willisms E.J. Holder USAF Rome Laboratory NY USA Statistical Signal and Image Processing LaboratoryDepartment of Electriical Engineering University of Southern California Los Angeles CA USA Digital Signal Processing LaboratorySchool of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

This paper is concerned with reducing the rank of the adaptive weight vector in radar array signal processing. The motivation for reducing the rank is that modern space-time processing requires many more weights than can be supported on airborne and space-segment platforms. The loss incurred in partially adaptive radar processing is that the steady-state Wiener solution of the lower rank weight vector may not perform as well as the full rank solution. Hence, this paper examines the Wiener solution of partially adaptive radar arrays and compares the performance of principal component techniques with the cross-spectral technique.

关键词： Radar signal processing Laboratories Adaptive arrays Space technology Steady-state Computational complexity Adaptive filters signal to noise ratio signal processing algorithms Contracts

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On balanced realizations of 2-D delta-operator formulated discrete-time systems

On balanced realizations of 2-D delta-operator formulated di...

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Southcon

作者： K. Premaratne M.M. Ekanayake P.H. Bauer Department of Electrical and Computer Engineering University of Miami Coral Gables FL USA Department of Electrical Engineering Laboratory of Image and Signal Analysis University of Notre Dame Notre Dame IN USA

Delta-operator based implementations can avoid the numerical ill-conditioning usually associated with the high speed shift-operator based implementations of discrete-time systems. Moreover, it provides a unified methodology for tackling both continuous- and discrete-time systems. In particular, it has been shown that, delta-operator based balanced realizations can offer superior coefficient sensitivity properties under fixed-point arithmetic. The authors address computation of balanced realizations. For this purpose, given a discrete-time system, the relationship between its shift- and delta-operator formulated balanced realizations is presented.

关键词： Fixed-point arithmetic Computational modeling Sampling methods Polynomials Laboratories signal analysis Computed tomography Eigenvalues and eigenfunctions Gold Stability

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