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37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology systems, DFT 2024

作者： Schwachhofer, Denis Domanski, Peter Becker, Steffen Wagner, Stefan Sauer, Matthias Pfluger, Dirk Polian, Ilia Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany Advantest Europe Boeblingen Germany

ISBN: (纸本)9798350366884

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description. © 2024 IEEE.

关键词： Functional Test Large Language Models Optimization System-Level Test Test Generation

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Fast and scalable in-network lock management using lock fission 24

Fast and scalable in-network lock management using lock fiss...

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Proceedings of the 18th USENIX Conference on Operating systems Design and Implementation

作者： Hanze Zhang Ke Cheng Rong Chen Haibo Chen Institute of Parallel and Distributed Systems SEIEE Shanghai Jiao Tong University and Shanghai AI Laboratory and MoE Key Lab of Artificial Intelligence AI Institute Shanghai Jiao Tong University Institute of Parallel and Distributed Systems SEIEE Shanghai Jiao Tong University and Engineering Research Center for Domain-specific Operating Systems Ministry of Education China Institute of Parallel and Distributed Systems SEIEE Shanghai Jiao Tong University and Shanghai AI Laboratory and Engineering Research Center for Domain-specific Operating Systems Ministry of Education China Institute of Parallel and Distributed Systems SEIEE Shanghai Jiao Tong University and Engineering Research Center for Domain-specific Operating Systems Ministry of Education China and Key Laboratory of System Software (Chinese Academy of Sciences)

ISBN: (纸本)9781939133403

distributed lock services are extensively utilized in distributed systems to serialize concurrent accesses to shared resources. The need for fast and scalable lock services has become more pronounced with decreasing task execution times and expanding dataset scales. However, traditional lock managers, reliant on server CPUs to handle lock requests, experience significant queuing delays in lock grant latency. Advanced network hardware (e.g. programmable switches) presents an avenue to manage locks without queuing delays due to their high packet processing power. Nevertheless, their constrained memory capacity restricts the manageable lock scale, thereby limiting their effect in large-scale *** paper presents FISSLOCK, a fast and scalable distributed lock service that exploits the programmable switch to improve (tail) latency and peak throughput for millions of locks. The key idea behind FISSLOCK is the concept of lock fission, which decouples lock management into grant decision and participant maintenance. FISSLOCK leverages the programmable switch to decide lock grants synchronously and relies on servers to maintain participants (i.e., holders and waiters) asynchronously. By using the programmable switch for routing, FISSLOCK enables on-demand fine-grained lock migration, thereby reducing the lock grant and release delays. FISSLOCK carefully designs and implements grant decision procedure on the programmable switch, supporting over one million locks. Evaluation using various benchmarks and a real-world application shows the efficiency of FISSLOCK. Compared to the state-of-the-art switch-based approach (NetLock), FISSLOCK cuts up to 79.1% (from 43.0%) of median lock grant time in the microbenchmark and improves transaction throughput for TATP and TPC-C by 1.76× and 2.28×, respectively.

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Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties

Training Large Language Models for System-Level Test Program...

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IEEE European Test Symposium (ETS)

作者： Denis Schwachhofer Peter Domanski Steffen Becker Stefan Wagner Matthias Sauer Dirk Pflüger Ilia Polian Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany Advantest Europe Boeblingen Germany

ISBN: (数字)9798350349320

ISBN: (纸本)9798350349337

System-Level Test (SLT) has been an integral part of integrated circuit test flows for over a decade and continues to be significant. Nevertheless, there is a lack of systematic approaches for generating test programs, specifically focusing on the non-functional aspects of the Device under Test (DUT). Currently, test engineers manually create test suites using commercially available software to simulate the end-user environment of the DUT. This process is challenging and laborious and does not assure adequate control over non-functional properties. This paper proposes to use Large Language Models (LLMs) for SLT program generation. We use a pre-trained LLM and fine-tune it to generate test programs that optimize non-functional properties of the DUT, e.g., instructions per cycle. Therefore, we use Gem5, a microarchitectural simulator, in conjunction with Reinforcement Learning-based training. Finally, we write a prompt to generate C code snippets that maximize the instructions per cycle of the given architecture. In addition, we apply hyperparameter optimization to achieve the best possible results in inference.

关键词： Training Knowledge engineering Codes Systematics Microarchitecture Process control Hyperparameter optimization

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Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties

arXiv

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arXiv 2024年

作者： Schwachhofer, Denis Domanski, Peter Becker, Steffen Wagner, Stefan Sauer, Matthias Pflüger, Dirk Polian, Ilia Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Advantest Europe Boeblingen Germany Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany

System-Level Test (SLT) has been a part of the test flow for integrated circuits for over a decade and still gains importance. However, no systematic approaches exist for test program generation, especially targeting non-functional properties of the Device under Test (DUT). Currently, test engineers manually compose test suites from off-the-shelf software, approximating the end-user environment of the DUT. This challenging and tedious task does not guarantee sufficient control over non-functional properties. This paper proposes Large Language Models (LLMs) to generate test programs. We take a first glance at how pre-trained LLMs perform in test program generation to optimize nonfunctional properties of the DUT. Therefore, we write a prompt to generate C code snippets that maximize the instructions per cycle of a super-scalar, out-of-order architecture in simulation. Additionally, we apply prompt and hyperparameter optimization to achieve the best possible results without further training. © 2024, CC BY.

关键词： software testing

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Large Language Model-Based Optimization for System-Level Test Program Generation

Large Language Model-Based Optimization for System-Level Tes...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI systems

ISBN: (数字)9798350366884

ISBN: (纸本)9798350366891

关键词： Measurement Schedules Codes Temperature Process control Very large scale integration software Optimization Nanotechnology Testing

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sNPU: Trusted Execution Environments on Integrated NPUs

sNPU: Trusted Execution Environments on Integrated NPUs

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Annual International Symposium on Computer Architecture, ISCA

作者： Erhu Feng Dahu Feng Dong Du Yubin Xia Haibo Chen Institute of Parallel and Distributed Systems SEIEE Shanghai Jiao Tong University Department of Precision Instrument Tsinghua University Engineering Research Center for Domain-specific Operating Systems Ministry of Education China Key Laboratory of System Software (Chinese Academy of Sciences)

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

Trusted execution environment (TEE) promises strong security guarantee with hardware extensions for security-sensitive tasks. Due to its numerous benefits, TEE has gained widespread adoption, and extended from CPU-only TEEs to FPGA and GPU TEE systems. However, existing TEE systems exhibit inadequate and inefficient support for an emerging (and significant) processing unit, NPU. For instance, commercial TEE systems resort to coarse-grained and static protection approaches for NPUs, resulting in notable performance degradation (10%–20%), limited (or no) multitasking capabilities, and suboptimal resource utilization. In this paper, we present a secure NPU architecture, known as sNPU, which aims to mitigate vulnerabilities inherent to the design of NPU architectures. First, sNPU proposes NPU Guarder to enhance the NPU’s access control. Second, sNPU defines new attack surfaces leveraging in-NPU structures like scratchpad and NoC, and designs NPU Isolator to guarantee the isolation of scratchpad and NoC routing. Third, our system introduces a trusted software module called NPU Monitor to minimize the software TCB. Our prototype, evaluated on FPGA, demonstrates that sNPU significantly mitigates the runtime costs associated with security checking (from upto 20% to 0%) while incurring less than 1% resource costs.

关键词： Costs Runtime Prototypes Computer architecture Routing software Resource management

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FEniCS-preCICE: Coupling FEniCS to other simulation software

arXiv

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arXiv 2021年

作者： Rodenberg, Benjamin Desai, Ishaan Hertrich, Richard Jaust, Alexander Uekermann, Benjamin Scientific Computing in Computer Science Department of Informatics Technical University of Munich Germany Usability and Sustainability of Simulation Software Institute for Parallel and Distributed Systems University of Stuttgart Germany Simulation of Large Systems Institute for Parallel and Distributed Systems University of Stuttgart Germany

The new software FEniCS-preCICE is a middle software layer, sitting in between the existing finite-element library FEniCS and the coupling library preCICE. The middle layer simplifies coupling (existing) FEniCS application codes to other simulation software via preCICE. To this end, FEniCS-preCICE converts between FEniCS and preCICE mesh and data structures, provides easy-to-use coupling conditions, and manages data checkpointing for implicit coupling. The new software is a library itself and follows a FEniCS-native style. Only a few lines of additional code are necessary to prepare a FEniCS application code for coupling. We illustrate the functionality of FEniCS-preCICE by two examples: a FEniCS heat conduction code coupled to OpenFOAM and a FEniCS linear elasticity code coupled to SU2. The results of both scenarios are compared with other simulation software showing good agreement. © 2021, CC BY-NC-ND.

关键词： Finite element method

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Predicting Eye Gaze Location on Websites

arXiv

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arXiv 2022年

作者： Zhang, Ciheng Aspandi, Decky Staab, Steffen Institute of Industrial Automation and Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Web and Internet Science University of Southampton Southampton United Kingdom

World-wide-web, with website and webpage as a main interface, facilitates dissemination of important information. Hence it is crucial to optimize webpage design for better user interaction, which is primarily done by analyzing users’ behavior, especially users’ eye-gaze locations on the webpage. However, gathering these data is still considered to be labor and time intensive. In this work, we enable the development of automatic eye-gaze estimations given webpage screenshots as input by curating of a unified dataset that consists of webpage screenshots, eye-gaze heatmap and website’s layout information in the form of image and text masks. Our curated dataset allows us to propose a deep learning-based model that leverages on both webpage screenshot and content information (image and text spatial location), which are then combined through attention mechanism for effective eye-gaze prediction. In our experiment, we show benefits of careful fine-tuning using our unified dataset to improve accuracy of eye-gaze predictions. We further observe the capability of our model to focus on targeted areas (images and text) to achieve accurate eye-gaze area predictions. Finally, comparison with other alternatives shows state-of-the-art result of our approach, establishing a benchmark for webpage based eye-gaze prediction task. © 2022, CC BY.

关键词： Websites

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A Flexible Digital Twin Framework for ATMP Production – Towards an efficient CAR T Cell Manufacturing

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Procedia CIRP 2024年 125卷 124-129页

作者： Arber Shoshi Yuchen Xia Andrea Fieschi Thomas Ackermann Peter Reimann Michael Weyrich Bernhard Mitschang Thomas Bauernhansl Robert Miehe Graduate School of Excellence advanced Manufacturing Engineering (GSaME) University of Stuttgart Nobelstraße 12 70569 Stuttgart Germany Fraunhofer Institute for Manufacturing Engineering and Automation (IPA) Nobelstraße 12 70569 Stuttgart Germany Institute of Industrial Automation and Software Engineering (IAS) University of Stuttgart Pfaffenwaldring 47 70550 Stuttgart Germany Institute for Parallel and Distributed Systems (IPVS) University of Stuttgart Universitätsstraße 38 70569 Stuttgart Germany Institute of Industrial Manufacturing and Management University of Stuttgart Allmandring 35 70569 Stuttgart Germany

This paper presents a flexible digital twin framework tailored for the biomanufacturing of advanced therapeutic medicinal products (ATMPs), particularly focusing on chimeric antigen receptor T cell (CAR T cell) therapy. CAR T cell therapies face significant challenges in the management of their personalized and complex biomanufacturing processes. To tackle these issues, we propose a novel software framework for a digital twin system aimed at digitalizing, monitoring, and managing the physical production processes. The framework has a hierarchical architecture that methodically organizes production into distinct abstraction levels: processes, tasks and skills, and microservices. This layered architecture simplifies the modeling of complex biomanufacturing production and ensures that each component can be individually updated without disrupting the overall system. Furthermore, the digital twin framework integrates both manual and automated operations within a unified system, accommodating varied requirements of diverse tasks in production. The framework’s flexibility enables easier adaptation to dynamic technological advancements and allows for swift modifications in production processes, making it a sustainable and resilient digitalization infrastructure for ATMP manufacturing.

关键词： ditgital twin ATMP CAR T cell production flexible software framework skill modeling

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科学研究的第五范式——以智能驱动的材料设计为例

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engineering 2023年第5期24卷 126-137,I0003,I0004页

作者： Can Leng Zhuo Tang Yi-Ge Zhou Zean Tian Wei-Qing Huang Jie Liu Keqin Li Kenli Li Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense TechnologyChangsha 410073China Laboratory of Software Engineering for Complex Systems National University of Defense TechnologyChangsha 410073China National Supercomputing Center in Changsha Changsha 410082China College of Computer Science and Electronic Engineering Hunan UniversityChangsha 410082China Institute of Chemical Biology and Nanomedicine State Key Laboratory of Chemo/Biosensing and ChemometricsCollege of Chemistry and Chemical EngineeringHunan UniversityChangsha 410082China Department of Applied Physics School of Physics and ElectronicsHunan UniversityChangsha 410082China Department of Computer Science State University of New YorkNew PaltzNY 12561USA

科学正在进入一个新时代——第五范式——它被认为是知识整合到不同领域的主要特征,是基于无所不在的机器学习系统的计算社区中智能驱动的工作。在此,我们通过在天河一号超级计算机系统上构建的催化材料专门设计的典型平台案例,生动地... 详细信息

科学正在进入一个新时代——第五范式——它被认为是知识整合到不同领域的主要特征,是基于无所不在的机器学习系统的计算社区中智能驱动的工作。在此,我们通过在天河一号超级计算机系统上构建的催化材料专门设计的典型平台案例,生动地阐明了第五范式的本质,旨在促进第五范式在其他领域的培养。第五范式平台主要包括模型自动构建(原始数据提取)、指纹自动构建(神经网络特征选择)以及跨学科知识串联的重复迭代(“火山图”)。与分解一起进行的是对迭代中实现的体系结构的性能评估。通过讨论,第五范式的智能驱动平台可以极大地简化和改进研究中极其繁琐和具有挑战性的工作,并通过补偿机器学习中缺少样本和替代一些由于计算资源不足而导致的数值计算来实现数值计算与机器学习之间的相互反馈,从而加速探索过程。在数据驱动的学科中,跨学科专家的协同作用和对动态数据需求的急剧增长仍然是一个挑战。我们相信,对第五范式平台的一瞥可以为其在其他领域的应用铺平道路。

关键词：机器学习自动构建天河一号数据驱动神经网络动态数据知识整合科学研究

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