The reduction of the energy consumption in the domain of the embedded systems is becoming the most important design goal due to the increasing use of battery powered consumer devices. Previous research has pointed out...
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Charge patterning on 1.3 μm-wide electret lines has successfully been demonstrated with a voltage of 80 V between charged Si_3N_4 lines and discharged unpatterned underlying SiO_2. The fabrication technology and char...
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ISBN:
(纸本)9781457717666
Charge patterning on 1.3 μm-wide electret lines has successfully been demonstrated with a voltage of 80 V between charged Si_3N_4 lines and discharged unpatterned underlying SiO_2. The fabrication technology and charge patterning methods were developed. A nine-month aging test on open air confirms that there is seemingly no dependence of charge retention time on line width within the 1 mm to 1.3 μm range. Accounting for the decay of surface potential during 9 months of aging, the charge lifetime in 1.3 μm-wide electret lines is about 40 years.
The reduction of the energy consumption in the domain of the embedded systems is becoming the most important design goal due to the increasing use of battery powered consumer devices. Previous research has pointed out...
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The reduction of the energy consumption in the domain of the embedded systems is becoming the most important design goal due to the increasing use of battery powered consumer devices. Previous research has pointed out the instruction memory organisation as one of the major sources of energy consumption of the embedded systems. Due to this fact, the introduction of any enhancement in this component of the system becomes crucial in order to decrease this energy bottleneck. The purpose of this paper is to present a highlevel energy analysis of the loop buffer schemes that exist in the embedded systems. The crucial energy analysis that is presented in this paper not only proposes a method to evaluate different loop buffer schemes for a certain application, but also guides embedded systems designers to make the correct decision in the trade-offs that exist between the energy budget, the required performance, and the area cost of the embedded system. Experimental results used in this analysis show that, the search of energy savings (up to 76%) has to take into account the performance penalty, the area cost, and the impact of the implementation technology in order to choose the most suitable enhancement that has to be introduced in the instruction memory organisation from the point of view of the energy consumption.
Nowadays, sub-45 nm designs are facing the challenges of parametric yield loss and reliability issues. Existing design practices increase the system's area/power penalty in order to cope with the growing number of...
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Nowadays, sub-45 nm designs are facing the challenges of parametric yield loss and reliability issues. Existing design practices increase the system's area/power penalty in order to cope with the growing number of design corners and their widening distributions. Our proposed solution is the Standardized Knobs and Monitors (SKM) framework, which enables monitoring and adjusting the circuits at run-time by utilizing power-delay trade-offs. More specifically, we focus on the systematic insertion of digital monitors at the RTL level of design abstraction and demonstrate our approach by using modified crystal ball delay monitor in a real-life wireless application.
The technology for in-plane poly-Si thermopiles has been developed. The bulkmicromachined thermopiles are located between two Si bars and connected thermally with those bars through thin-film thermal shunts. The patte...
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Single transistor Floating Body Random Access Memories (FB-RAMs) are foreseen to bring size and speed benefits and have the potential to replace existing DRAMs. However, the implementation in matrix is complex because...
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Single transistor Floating Body Random Access Memories (FB-RAMs) are foreseen to bring size and speed benefits and have the potential to replace existing DRAMs. However, the implementation in matrix is complex because the voltages applied to access one cell can disturb the state of other cells. We propose an approach at circuit level to provide compatible bias conditions and to explore further on the optimization of the biasing voltages for improved write and read operations and improved retention. To do so we use synchronized bitline and wordline drivers providing different voltages to selected and unselected lines during the different operations. In addition, a robust sensing scheme is described that can be implemented in the same process technology as the array. The full circuit has been validated by simulations based on the experimental data of fabricated bulk FinFETs floating body cells and the design has been taped out.
Integration of thermopiles in garments has been performed in this work in different ways. It is shown that textile has a minor effect on power generation, which enables completely hidden and unobtrusive energy harvest...
Integration of thermopiles in garments has been performed in this work in different ways. It is shown that textile has a minor effect on power generation, which enables completely hidden and unobtrusive energy harvester. A one-milliwatt thermoelectric generator is then integrated between two layers of a shirt and its characteristics are reported.
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