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5th International Conference on IoT Based Control Networks and Intelligent Systems, ICICNIS 2024

作者： Gopi Arepalli, Peda Maneesha, K. Srija, M. Sadifbanu, T. Sk. Likhitha, T. Tumati, Ramakrishna Vignan's Nirula Institute of Technology and Science for Women Department of CSE Palakaluru Pedha Guntur India Software Application Development Engineer Intel

ISBN: (纸本)9798331518097

A novel technique in early Parkinson's disease diagnosis with the use of a quantum long short-term memory model is described in this paper. Quantum computing, therefore, coupled with deep learning, seeks to improve the accuracy as well as efficiency of classifying traditional LSTM models, which even becomes more critical in cases of neurodegenerative diseases like Parkinson's disease, where diagnostics at an early stage would be helpful. The model was tested heavily on public datasets and compared with traditional deep learning models, which were significantly outperformed by this model with its superior accuracy and precision and recall rates. Furthermore, the computation time hugely became lower and thus possibly may revolutionize diagnostic procedures. These innovations will eventually establish quantum machine learning in medicine at a more accurate and faster diagnosis pace. Future development will focus on expanding the quantum LSTM so it can be more generally applicable to various situations for other medical conditions. Researchers believe that the configuration of the quantum layers should be modified, and this model will be extended to other deep learning models to have a more comprehensive and versatile tool in diagnosis for Parkinson's disease and perhaps other medical uses. The ultimate vision in the long term would be to use quantum-based models, not only for early detection but also improvement in prediction and personalization of treatment to revolutionize health care and thereby improve patient outcomes with neurodegenerative diseases. © 2024 IEEE.

关键词： Neurodegenerative diseases

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Convolution Neural Network for Fault Detection and Classification in Hybrid Overhead-Underground Distribution System 3

Convolution Neural Network for Fault Detection and Classific...

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3rd International Conference on Power, Control and Computing Technologies, ICPC2T 2024

作者： Nag, Ankita Yadav, Anamika Gupta, Shubhrata Software Application Development Engineer Intel Corporation DallasTX United States Institute of Technology Raipur Electrical Engineering Department National Raipur India

ISBN: (纸本)9798350349207

In distribution systems, a trend to use overhead (OH) lines along with underground (UG) cable is becoming popular due to densely populated areas which give rise to right of way and public safety issues. In these complex systems, maintaining continuous power supply and early detection and clearance of the fault are challenging tasks. Feature extraction from fault signals is the main concern of all detection schemes during occurrence of a fault. This article presents a Convolution Neural Network (CNN) which is a single learning body to detect faults in hybrid OH-UG cable. CNN rules are superior to other pattern-recognition techniques since they extract features and simultaneously detect faults as a single entity. The hybrid distribution system is simulated using MATLAB and the proposed scheme is compared with different soft computing techniques. © 2024 IEEE.

关键词： Fault detection

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Image-Based Malware Classification Powered by Deep Learning based DenseNet-121 for Enhancing Cybersecurity

Image-Based Malware Classification Powered by Deep Learning ...

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Advancement in Computation & Computer Technologies (InCACCT), International Conference on

作者： Ramakrishna Tumati Peda Gopi Arepalli Software Application Development Engineer Intel USA Department of CSE Vignan’s Nirula Institute of Technology and Science for Women Guntur

ISBN: (数字)9798331543891

ISBN: (纸本)9798331543907

Cybersecurity is threatened by the increased number of malware and the growing emergence of sophisticated malware types. Traditional anti-malware software, commonly binarily dependent, cannot effectively cope with new and disguised threats. In this paper, authors investigate the possibility of rank-based image classification of malware using DenseNet-121 within the context of the Malimg dataset. The malware binaries introduced here are instead transformed into grayscale images: this way, the task becomes an image classification, where the model is capable of distinguishing fine features and structures which are distinctive of families of malware. DenseNet-121 uses a densely connection which enables feature propagation, reduces vanishing gradient and improves the representation learning since the features are reused at different levels. Numerous experiments on the Malimg dataset show that DenseNet-121 performs with high accuracy and is less sensitive to dataset bias than the other models in the field. The work further explores the effects of several preprocessing methods, data augmentation, and hypers parameter optimization on the model results. The results further emphasize the effectiveness of image-based analysis as a supplementary approach to malware detection, which is extendable and malleable against the emerging malicious software threats.

关键词： Deep learning Representation learning Accuracy Computer architecture Feature extraction Malware Computer security Tuning Optimization Image classification

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Parkinson's Disease Detection Using Q-LSTM

Parkinson's Disease Detection Using Q-LSTM

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IoT Based Control Networks and Intelligent Systems (ICICNIS), International Conference on

作者： Peda Gopi Arepalli K. Maneesha M. Srija T. Sk. SadifBanu T. Likhitha Ramakrishna Tumati Department of CSE Vignan's Nirula Institute of Technology and Science for Women PedhaPalakaluru Guntur Software application development engineer Intel

ISBN: (数字)9798331518097

ISBN: (纸本)9798331518103

关键词： Deep learning Technological innovation Quantum computing Accuracy Parkinson's disease Computational modeling Predictive models Long short term memory Medical diagnostic imaging Tuning

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Two-Level Biometric Security System for Voting 2

Two-Level Biometric Security System for Voting

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2nd International Conference on Smart Electronics and Communication, ICOSEC 2021

作者： Srivastva, Snigdha Kalra, Yashika Chavan, Akshay Jagtap, Gaurav DXC Technology Software Engineer Application Development Associate Accenture Quantiphi Analytics DRDO Govt. of India Mechanical Design Engineer

ISBN: (纸本)9781665433686

There is a lot of controversy in India during the election process, including multiple voting, fake voting, etc. This research is to help develop a system to eradicate such disputes. To improve the voting process's security performance, voters' fingerprints are used as any person can be uniquely identified by matching their fingerprints, including several levels of verification to make sure the authenticity of this process. Hence, registration, enrollment and voting scheme's authenticity can be secured in the best way using a biometric voting system. A combination of matching algorithms is used for determining a match for the input data. The voter is supposed to go for biometric verification before entering the voting booth to eradicate any chance of multiple voting, thus ensuring the purpose of 'One Voter- One Vote' [3]. Subsequently, all the voters match their fingerprint samples against the database's values during the confirmation time frame. © 2021 IEEE.

关键词： Biometrics

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Convolution Neural Network for Fault Detection and Classification in Hybrid Overhead-Underground Distribution System

Convolution Neural Network for Fault Detection and Classific...

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Power, Control and Computing Technologies (ICPC2T), Conference on

作者： Ankita Nag Anamika Yadav Shubhrata Gupta Software Application Development Engineer Intel Corporation Dallas Texas U.S.A. Electrical Engineering Department National Institute of Technology Raipur Raipur India

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Survey of reduced workload and crewing strategies for ocean patrol vessels

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NAVAL engineerS JOURNAL 2001年第2期113卷 29-44页

作者： Baker, C Krull, R Snyder, G Lincoln, W Malone, TB Clifford C. Baker CIE CHFEP is a senior staff scientist at Carlow International Incorporated. He has applied most of his 24 years of experience in the application of human engineering technology to maritime systems. Mr. Baker has directed much of Carlow's efforts to reduce ship workload and to improve human performance and maritime safety through application of human factors methods and data. He is a Certified Industrial Ergonomist (CIE) as well as a Certified Human Factors Engineering Professional (CHFEP). Both certifications were granted by Oxford Research where Mr. Baker also serves as an Advisory Board member. Russell D. Krull P.E. is a senior engineer with A&T/Proteus Engineering with more than 18 years of experi-ence in marine engineering naval architecture and program management including 16 years of active duty in the U.S. Coast Guard. Recent experience includes advanced ship design studies engineering software development technical support for the USMC Advanced Amphibious Assault Vehicle propulsion systems analyses ship structural engineering and cargo handling systems engineering. Mr. Krull has an M.S.E. in naval architecture and marine engineering and an M.S.E. in industrial and operations engineering from University of Michigan and a B.S. in ocean engineering from the U.S. Coast Guard Academy. Capt. Glenn L. Snyder USCG. Regrettably since this paper was originally written Capt. Snyder has passed away. At the time of his death he was an operations specialist assigned to the Coast Guard's Deepwater Capabilities Replacement Project as Chief of Human Systems Integration. He served as commanding officer of the patrol boat Cape George (WPB-95306) the icebreaking tug Biscayne Bay (WTGB-104) and the cutter Legare (WMEC-911). A 1975 graduate of the U.S. Coast Guard Academy Capt. Snyder held an M.A. in national security and strategic studies from the U.S. Naval War College and an M.A. in international relations from Salve Regina College. In addition he was a 1998 fellow of the Foreign Service

The U.S. Coast Guard is in the concept exploration phase of its Integrated Deepwater System (IDS) acquisition project. This project will define the next generation of surface, air and command, control, communications, computers, intelligence, surveillance, and reconnaissance (C4ISR) assets used to perform the Coast Guard's missions in the IDS environment (>50 NM off the U. S. coastline). As part of early technology investigations, the needs exist to: (1) analyze the workload requirements of the IDS, (2) identify alternative means to perform ship's work, and (3) optimize ship manning consistent with ship workload, performance criteria, and the available tools and equipment aboard. To reduce shipboard work requires an understanding of the mission and support requirements placed on the vessel and crew, how these requirements are currently met, and how requirements might otherwise be met to reduce workload and crew size. This study examined currently implemented workload and manpower reducing approaches of commercial maritime fleets, U.S. and foreign navies, and foreign coastguards. These approaches were analyzed according to evaluation criteria approved by the IDS acquisition project team. From this, strategies for shipboard work reduction that may be considered for adoption by the IDS were identified and analyzed according to performance and costs factors. Ten workload-reducing strategies were identified: damage control, bridge, multiple crewing, engineering, risk acceptance, modularity, deck, enabling technologies, ship/personnel readiness, and operability and maintainability.

关键词： Naval vessels

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A high-speed high-density array-multiplier-accumulator for digital signal processing

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ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 1996年第2期79卷 86-97页

作者： Minami, T Kasai, R Matsuda, H Kusaba, R Member NTT LSI Laboratories Atsugi Japan 243-01 Graduated in 1980 from the Department of Electrical Engineering Kyushu University where he received his Master's degree in 1982 and joined NTT. Until March 1986 he was engaged in the development of application software for electronic switching systems. He then engaged in research and development of LSIs for image signal processing. At present he is Senior Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of IEEE. Graduated in 1972 from the Department of Electrical Engineering Osaka University where he received his Master's degree in 1974 and his Ph.D. in 1992. He joined NTT in 1974. He is engaged in research and development of analysis of MOS devices and design of ASIC for communication. At present he is Executive Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of IEEE. Graduated in 1987 from the Department of Communications Tohoku University where he received his Master's degree in 1989 and joined NTT. He is engaged in research and development of high-speed design for image processing LSIs. At present he is Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of the Information Processing Society. Graduated in 1985 from the Department of Electrical Engineering Keio University where he received his Master's degree in 1987 and joined NTT. He is engaged in CAD research. At present he is Senior Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of the Information Processing Society and IEEE.

This paper discusses the downsizing and speed improvement of short-word multiplier-accumulators, which are frequently used in digital signal processors. As a first step, the optimal configuration for an array-type carry-save adder is considered where the shortest path in the full-adder is used to propagate the sum signal and the carry signal is sent to the full-adder of the two lower stages by skipping a stage. A configuration of the full-adder suitable for the structure is proposed. The case of eight partial product additions shows that the delay can be reduced by 22 percent compared to a simple array-type carry-save adder. Then the short-word carry look-ahead adder using the pass-transistor logic is considered. It is shown that a single-stage carry look-ahead circuit with a four-bitwise iterative structure exhibits nearly the same delay as a two-stage carry look-ahead circuit. In other words, the former is better suited to downsizing. This paper intends to examine the effectiveness of the foregoing new array-type carry-save adder and the single-stage carry look-ahead circuit using the 0.5-mu m CMOS technology. A 16-bit x 14-bit + 31-bit multiplier-accumulator has been designed and is evaluated for cases where the array-type carry-save adder is used to handle accumulation as well as partial products. The resulting area and delay are 0.77 x 0.78 mm(2) and 6.8 ns, respectively. The effectiveness of the approach used in this paper is evaluated by constructing a multiplier-accumulator, but the method is also useful in constructing a multiplier.

关键词： product-sum operation array multiplier carry-save adder full-adder carry look-ahead adder

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UTILIZING RESERVE ASSETS - MUTUAL SUPPORT AT SUPSHIP BATH

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NAVAL engineerS JOURNAL 1993年第6期105卷 39-42页

作者： GOLDA, EM PORPORA, GA Cdr. Eugene Michael Golda:is a Naval Reserve engineering duty officer and is commanding officer of NR NavSea PMS Det 302. He has developed and directed mutual support programs assisting the Supervisor of Shipbuilding Brooklyn and has participated in the training and mutual support programs at the Supervisor of Shipbuilding Bath. He received a Ph.D. and M.S. in materials science and engineering from Stevens Institute of Technology Hoboken N.J. A 1977 graduate of the United States Naval Academy Cdr. Golda has been a member of ASNE since 1974. Cdr. Golda is a materials engineer at the Annapolis Detachment Carderock Division Naval Surface Warfare Center working on naval applications of superconducting technology. LCdr. Gregory A. Porpora:is an IBM market support representative who provides technical consulting support in application development with computer aided software engineering (CASE) tools. Prior to joining IBM he was a senior design engineer for a defense contractor involved in design and development of radar and ASW systems including the AN/BSY-1 combat system trainer. LCdr. Porpora is a member of IEEE the Naval Institute and the Naval Reserve Association. He holds a BSEE and MSEE from the Polytechnic Institute of Technology New York. LCdr. Porpora is currently assigned to NR SupShip Det 502 which provides extensive mutual support for the Supervisor of Shipbuilding Bath and the resident office in Brooklyn New York.

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CAD CAM MANUFACTURING OF PROTOTYPE SHIPBOARD COMPONENTS

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NAVAL engineerS JOURNAL 1990年第3期102卷 93-99页

作者： CALVERT, TE RODRIGUEZ, FA SLEBZAK, JS Thomas E. Calvert P.E.: is a senior project engineer with the Propulsion and Auxiliary Systems Department David Taylor Research Center Annapolis Md. His interests include application of computers to all aspects of engineering with particular emphasis on utilization of small computers. Mr. Calvert is a licensed professional engineer in Maryland. He received a BSEE from Drexel University in 1969 and since that time has completed a number of graduate courses related to machinery acoustics. Francisco A. Rodriguez:is an engineer with the Propulsion and Auxiliary Systems Department David Taylor Research Center. He was formerly with the Computer-Aided Design/Interactive Graphics Group of the Division of Engineering and Weapons U.S. Naval Academy. His interests include interfacing the computer aided design to the computer aided manufacturing along with related software and hardware development. Mr. Rodriguez received a BSEEfrom the University of Virginia in 1968. James S. Slebzak:is a mechanical engineering technician with the Propulsion and Auxiliary Systems Department David Taylor Research Center. He received his machinists papers in 1971 after serving his apprenticeship at David Taylor Research Center. He continued his education and became the senior numerical control programmer at the Annapolis Laboratory. He completed his mechanical technology degree from Anne Arundel Community College in 1986. His interests are in the application of numerically controlled manufacturing techniques to prototype machinery components.

The machine shop at the Annapolis Laboratory of the David Taylor Research Center (DTRC) provides model making and prototype support to a large variety of naval ship related engineering projects. In order to meet these challenging requirements, computer aided design/computer aided manufacturing (CAD/CAM) techniques are being used to produce “one of a kind” prototypes or very low volume production parts. The use of computer aides in these cases is to facilitate the accurate manufacture of a difficult part, rather than to improve manufacturing efficiencies. In addition, the approach provides the flexibility required to support research and development projects. Several examples of prototype shipboard components manufactured using CAD/CAM techniques are presented in this paper. The hardware and software that facilitated these projects are discussed. The examples described have met the requirements to produce a wide variety of prototype shipboard machinery components quickly and accurately.

关键词： Ship Equipment

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