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A distributed I/O architecture for HARTS

A distributed I/O architecture for HARTS

引用

Annual International Symposium on Computer Architecture, ISCA

作者： K.G. Shin G. Dykema Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The issue of I/O device access in HARTS (Hexagonal Architecture for real-time Systems)-a distributed real-time computer system under construction at the University of Michigan-is explicitly addressed. Several candidate solutions are introduced, explored and evaluated according to cost, complexity, reliability, and performance: (1) 'node-direct' distribution with the intranode bus and a local I/O bus; (2) use of dedicated I/O nodes, which are placed in the hexagonal mesh as regular applications nodes, but which provide I/O services rather than computing services; and (3) use of a separate I/O network; which has led to the proposal of an 'interlaced' I/O network. The interlaced I/O network is intended to provide both high performance without burdening node processors with I/O overhead and a high degree of reliability. Both static and dynamic multiownership protocols are developed for managing I/O device access in this I/O network. The relative merits of the two protocols are explored, and the performance and accessibility which each provides are simulated.< >

关键词： real time systems Distributed computing Topology Computer architecture Laboratories Costs Proposals Access protocols Hypercubes Computer networks

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Design of a Knowledge-Based Controller for Intelligent Control Systems

Design of a Knowledge-Based Controller for Intelligent Contr...

引用

American Control Conference (ACC)

作者： Kang G. Shin Xianzhong Cui Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A hierarchical knowledge-based controller is proposed to improve the performance of complex control systems, such as robots. Unlike parameter- and performance- adaptive controllers, this controller is designed only to modify the reference input of a low-level servo controller. Because the internal parameters and structure of the low-level controller are not affected, commercial servo controllers can be made to perform more sophisticated tasks than originally intended. The principle of the knowledge-based controller, modification of the reference input, knowledge representation, existence of the solution, and analyses of the controller's stability and tracking error are described in detail. A self-tuning multiple-step predictor is designed as a part of the controller to eliminate the undesirable effects of system time delay. Both linear and nonlinear example control systems are tested via extensive simulations and have all shown promising performances.

关键词： Control systems Intelligent control Servomechanisms Robots Programmable control Adaptive control Knowledge representation Stability analysis Error correction Delay effects

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Load Sharing In Hypercube Multicomputers In The Presence Of Node Failures

Load Sharing In Hypercube Multicomputers In The Presence Of ...

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Distributed Memory computing Conference

作者： Yi-Chieh Chang Kang G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

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Shortest path planning with dominance relation

Shortest path planning with dominance relation

引用

IEEE International Conference on Robotics and Automation (ICRA)

作者： S. Jun K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A method of partitioning a workspace using rectilinear visibility in 3-D or higher space is presented. Unlike the case of 2-D space, where the space of a partition is a rectangle, the shape of a partition in 3-D or higher space is arbitrary. In spite of the arbitrary shape of partitioned regions, it is proved that there exist dominance relations between regions. This relation is then utilized to solve efficiently the shortest path planning problem in 3-D or higher space.< >

关键词： Path planning Shape Costs Application software Manipulators Laboratories Remotely operated vehicles Mobile robots Routing Very large scale integration

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Scheduling job operations in an automatic assembly line

Scheduling job operations in an automatic assembly line

引用

IEEE International Conference on Robotics and Automation (ICRA)

作者： K.G. Shin Q. Zheng Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The problem of scheduling job operations in an automatic assembly line used for manufacturing a small to medium volume of mixed workparts is addressed. The assembly line model differs from the classical flow shop model in the following three aspects: (1) there are no buffers at machine stations, (2) constraints associated with the material transport system are included, and (3) for each batch production, workparts are distinguished in groups, rather than individually. An optimal algorithm that requires very little computation is derived by minimizing the total finish time for two machine assembly lines. This result is generalized to the problem of scheduling an assembly line with m>2 machines processing single-operation jobs. In order to reduce the computational complexity of the latter problem, heuristic algorithms are also proposed and shown to work quite well for all the cases considered. The solution to the problem of scheduling an assembly line with m>2 machines processing multioperation jobs is discussed.< >

关键词： Assembly Job shop scheduling Processor scheduling Pulp manufacturing Flexible manufacturing systems Optimal scheduling Manufacturing automation Heuristic algorithms Scheduling algorithm Laboratories

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Analysis of three contention protocols in distributed real-time systems

Analysis of three contention protocols in distributed real-t...

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real-time Systems Symposium (RTSS)

作者： K.G. Shin C.-J. Hou Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The probability of a station/node failing to deliver packets before their deadlines, called the probability of dynamic failure, P/sub dyn/, and the in -bounded delivery time, which is defined as the time period between the arrival of a packet and its delivery with probability greater than 1- in , are important performance parameters for the communication subsystems of a distributed real-time system. The parameters are derived and are used to evaluate the token passing protocol, the token ring scheduling protocol, and the P/sub i/-persistent protocol and a priority-based variation thereof. The communication subsystem equipped with different contention protocols as embedded Markov chains is modeled. The probability distributions of the access delay are then derived, from which P/sub dyn/ and T/sub in / can be calculated. Using P/sub dyn/ and I/sub in / as indices, the performances of these contention protocols are evaluated and compared over a wide range of traffic.< >

关键词： real time systems Access protocols Token networks Delay Timing Distributed computing Throughput Multiaccess communication Chaotic communication Laboratories

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Optimal multiple syndrome probabilistic diagnosis

Optimal multiple syndrome probabilistic diagnosis

引用

International Symposium on Fault-Tolerant computing (FTCS)

作者： S. Lee K.G. Shin Department of Electrical Engineering University of Delaware Newark DE USA Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors discuss the distributed self-diagnosis of a multiprocessor/multicomputer system based on interprocessor tests with imperfect fault coverage (thus also permitting intermittently fault processors). It is shown that by using multiple fault syndromes, it is possible to achieve significantly better diagnosis than by using a single fault syndrome, even when the amount of time devoted to testing is the same. The authors derive a multiple syndrome diagnosis algorithm that is optimal in the level of diagnostic accuracy achieved (among diagnosis algorithms of a certain type to be defined) and produces good results even with sparse interconnection networks and interprocessor test with low fault coverage. Furthermore, they prove upper and lower bounds are proved on the number of fault syndromes required to produce asymptotically a 100% correct diagnostic as N to infinity . Their solution and another multiple syndrome diagnosis solution by D. Fussell and S. Rangarajan are evaluated both analytically and with simulations.< >

关键词： Fault diagnosis System testing Upper bound Multiprocessing systems Automatic testing Multiprocessor interconnection networks Analytical models Algorithm design and analysis H infinity control Laboratories

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A Bayesian approach to fault classification 90

A Bayesian approach to fault classification

引用

Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems

作者： Tein-Hsiang Lin Kang G. Shin Department of Electrical and Computer Engineering State University of New York at Buffalo Buffalo New York Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor Michigan

ISBN: (纸本)9780897913591

According to their temporal behavior, faults in computer systems are classified into permanent, intermittent, and transient faults. Since it is impossible to identify the type of a fault upon its first detection, the common practice is to retry the failed instruction one or more times and then use other fault recovery methods, such as rollback or restart, if the retry is not successful. To determine an “optimal” (in some sense) number of retries, we need to know several fault parameters, which can be estimated only after classifying all the faults detected in the *** this paper we propose a new fault classification scheme which assigns a fault type to each detected fault based on its detection time, the outcome of retry, and its detection symptom. This classification procedure utilizes the Bayesian decision theory to sequentially update the estimation of fault parameters whenever a detected fault is classified. An important advantage of this classification is the early identification of presence of an intermittent fault so that appropriate measures can be taken before it causes a serious damage to the system. To assess the goodness of the proposed scheme, the probability of incorrect classification is also analyzed and compared with simulation results.

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Message routing in HARTS with faulty components

Message routing in HARTS with faulty components

引用

International Symposium on Fault-Tolerant computing (FTCS)

作者： A. Olson K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors develop a routing scheme in two steps for a wrapped hexagonal mesh, called HARTS (hexagonal architecture for real-time systems), which ensures the delivery of every message as long as there is a path between its source and destination. The scheme can also detect the nonexistence of a path between a pair of nodes in a finite amount of time. Moreover, the scheme requires each node in HARTS to know only the state (faulty or not) of each of its own links. The performance of the simple routing scheme is simulated for three- and five-dimensional H-meshes while the physical distribution of faulty components is varied. It is shown that a shortest path between the source and the destination of each message is taken with a high probability, and a path, if one exists, is usually found very quickly.< >

关键词： Routing Laboratories Fault tolerant systems Computational modeling Distributed computing Parallel processing Hypercubes Broadcasting NASA Contracts

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An efficient design of embedded memories and their testability analysis using Markov chains

An efficient design of embedded memories and their testabili...

引用

International Conference on Wafer Scale Integration

作者： P. Mazumder Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM), where the address, read/write, and data input lines are not directly controllable and the data output lines are not externally observable, is presented. Unlike conventional approaches which use a linear feedback shift register (LFSR) to generate a signature and a register to store the reference fault-free signature, this technique uses a testable design which both accelerates the test by a factor of 0.5 square root n in an n-bit RAM and improves the test reliability by eliminating the LFSR. The problem of memory initialization has been elegantly circumvented by using word-line flag registers. An in-depth and comprehensive analysis of the functional faults, such as stuck-at, coupling, and pattern-sensitive, is performed. The analysis shows that, in order to test a 1-Mb RAM for common functional faults, the technique needs only 1 s, as opposed to about an hour needed by the conventional random testing.< >

关键词： Random access memory Circuit testing Read-write memory Circuit faults Registers Built-in self-test Life estimation Vectors Gold Sequential analysis

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