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A module-sliced approach for high yield VLSI/WSI processors

A module-sliced approach for high yield VLSI/WSI processors

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Y.-C. Chang K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The module-sliced approach is realized in a reconfigurable fault-tolerant segmented array processor (RFTSAP). The basic building block of RFTSAP is a node which consists of a processor, local memory, and a programmable I/O unit (PIOU). The PIOU allows any group of processors to be combined to perform the functions of a large processor module. The yield of a large processor module can be improved 2 to 4 times compared to that of approaches not using the module-sliced method.< >

关键词： Very large scale integration Switches Microprocessors Fault tolerance Registers Strontium Laboratories Redundancy Process control Computer architecture

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Minimum time trajectory planning for dual robot systems

Minimum time trajectory planning for dual robot systems

引用

IEEE Conference on Decision and Control

作者： K.G. Shin Q. Zheng Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The problem of planning minimum time collision-free trajectories for a dual robot system is addressed. It is shown that this problem can be solved by first planning the minimum time trajectory for each robot without considering the existence of the other and then combining the two individual trajectories. This combination is accomplished by delaying one of the two trajectories in such a way that the time required for the coordinated motion of the two robots is minimized while avoiding collision between them. The optimality of the method is rigorously proved, the practical aspects of its realization are discussed, and example is presented.< >

关键词： Trajectory Robot kinematics Path planning Robot sensing systems Motion planning Laboratories Computer science Delay effects Artificial intelligence Productivity

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Message communications in a distributed real-time system with a polled bus

Message communications in a distributed real-time system wit...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： K.G. Shin Y. Muthuswamy Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

High-speed message communications is addressed. Each node in the system consists of multiple processors interconnected by a broadcast bus, but the individual nodes are interconnected by an arbitrary network. The concept of a poll number is proposed to control the access to an intranode bus, minimizing the probability of real-time messages missing their deadlines. When a task generates a time-constrained message, a poll number associated with the message is computed on the basis of the message deadline and the task priority. When the bus is free, the various tasks at a node which desire to use the bus write the poll number onto the bus and read it back, one bit at a time, starting from the most significant bit. If at any time the bit read back is different from the bit written, then that particular task drops out of the competition for the bus. The mechanism provides for not only decentralized control of the intranode bus, but also a high degree of flexibility in scheduling messages by different ways of generating poll numbers. The probability of a message missing its deadline in a token bus is found to be much higher than in a polled bus.< >

关键词： real time systems Communication system control Control systems time factors Automatic control Process control Laboratories Broadcasting Distributed control Job shop scheduling

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Static allocation of periodic tasks with precedence constraints in distributed real-time systems

Static allocation of periodic tasks with precedence constrai...

引用

International Conference on Distributed computing Systems

作者： D.-T. Peng K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Using two branch-and-bound (B&B) algorithms, an optimal solution is proposed to the problem of allocating (or assigning with the subsequent scheduling considered) periodic tasks to a set of heterogeneous processing nodes (PNs) of a distributed real-time system. The allocation objective is to minimize the maximum normalized task response time, called the system hazard, subject to precedence constraints among the tasks to be allocated. First, the task system is modeled with a task graph, which describes computation and communication modules as well as the precedence constraints among them. Second, the exact system hazard of a complete assignment is determined so that an optimal assignment can be derived. This exact cost is obtained by optimally scheduling the modules assigned to each PN with a B&B algorithm guided by the dominance relationship between simultaneously schedulable modules. Third, to reduce the amount of computation needed for an optimal assignment, a lower-bound system hazard that is obtainable with a polynomial time algorithm is derived.< >

关键词： real time systems Scheduling algorithm Delay Processor scheduling Hazards Cost function Distributed computing Laboratories Polynomials time factors

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A floating communication processor architecture in a distributed real-time system

A floating communication processor architecture in a distrib...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： K.G. Shin Y. Muthuswamy Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The issues involved in providing hardware communication support at each mode in a distributed real-time system are studied. First, a general architecture for each node of the system is described. An algorithm for message handling by dedicated hardware called a communication processor (CP) is proposed, to maximize the number of requests handled over the various constraints. A floating CP architecture is proposed, to maximize the number of requests handled under the various constraints. A floating CP architecture is proposed to maximize the utilization of the processors at a node and provide greater fault-tolerance in the system.< >

关键词： real time systems Hardware Computer architecture Distributed computing Concurrent computing Laboratories Fault tolerant systems Message passing Data structures Bandwidth

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A microprogrammable VLSI routing controller for HARTS

A microprogrammable VLSI routing controller for HARTS

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： J.W. Dolter P. Ramanathan K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The design and implementation of a VLSI routing controller for use in the Hexagonal Architecture for real-time Systems (HARTS), which is currently being built, are presented. The routing controller is a microprogrammed unit designed to function as an intelligent front-end interface for the interconnection network. Unlike other routine controllers known to date, this routing controller allows for the flexibility to investigate several low-level routing algorithms by downloading the appropriate microcode into the routing controller. The design was carried out using the combination of Seattle Silicon Technology's silicon compiler and Mentor Graphic's schematic capture and simulation tools. The implementation is targeted for a 64-pin package using a 1.2- mu m CMOS process.< >

关键词： Very large scale integration Routing Control systems real time systems Intelligent networks Multiprocessor interconnection networks CMOS technology Silicon compiler Packaging CMOS process

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A clock distribution scheme for nonsymmetric VLSI circuits

A clock distribution scheme for nonsymmetric VLSI circuits

引用

IEEE International Conference on Computer-Aided Design

作者： P. Ramanathan K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors propose a clock distribution scheme that minimizes the difference in the length of clock lines, which is the foremost factor responsible for clock skew in a VLSI circuit. The scheme uses the hierarchy created by the clock buffers to parallelize the distribution of the clock signal. At each hierarchical level, an exhaustive search of paths with intelligent pruning is used to determine the optimal layout of clock lines at that level. Unlike other related work in this area, both delay and skew are taken into account in determining the layout.< >

关键词： Clocks Very large scale integration Circuits Delay Timing Uncertainty NASA Laboratories Control systems Digital systems

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Task Migration In Hypercube Multiprocessors

Task Migration In Hypercube Multiprocessors

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Annual International Symposium on Computer Architecture, ISCA

作者： Ming-Syan Chen Kang G. Shin The University of Michigan Department of Electrical Engineering and Computer Science Real-Time Computing Laboratory University슠of슠Michigan Ann Arbor MI USA

Allocation and deallocation of subcubes usually result in a fragmented hypercube where even if a sufficient number of hypercube nodes are available, they do not form a subeube large enough to execute an incoming task. As the fragmentation in conventional memory allocation can be handled by memory compaction, the fragmentation problem in a hypercube can be solved by task migration, i.e., relocating tasks within the hypercubc to remove the fragmentation. The procedure for task migration closely depends on the subcube allocation strategy used, since active tasks must be relocated in such a way that the availability of subcubcs can be detected by that allocation strategy. In this paper, we develop a task migration strategy for the sub cube allocation policy based on the binary reflected Gray code. A goal configuration (of destination subeubes) without fragmentation is determined first. Then, the node-mapping between the source and destination subcubes is derived. Finally, a routing procedure to achieve shortest deadlock-free paths for relocating tasks is developed.

关键词： Hypercubes Permission Compaction Reflective binary codes Laboratories Routing System recovery Concurrent computing Computer industry Encoding

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Hypercube management in the presence of node failures 3

Hypercube management in the presence of node failures

引用

3rd Conference on Hypercube Concurrent Computers and Applications, C3P 1988

作者： Kandlur, Dilip D. Shin, Kang G. Real-time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0897912780

The problem of allocation and release of subcubes from a hypercube with node failures is addressed. Two algorithms are presented, both based on the Buddy allocation scheme for memory management which is also used by the AXIS operating system of the NCUBE hypercube computer. The first algorithm is a simple variation of the Buddy algorithm which permits the efficient allocation of subcubes in the presence of a single faulty node. The second algorithm, which effectively subsumes the first, tries to reduce the fragmentation caused by multiple failed nodes. It uses a relabeling scheme to group the failed nodes so that large non-faulty subcubes can be detected using the Buddy allocation scheme. The relative performance of these algorithms is studied using simulation and the proposed algorithms are shown to have a consistently better performance. Issues relating to the detection of faulty nodes on the NCUBE computer and the consequences of the relabeling on message passing are also discussed. © ACM 1988.

关键词： Message passing

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Embedding triple-modular redundancy into a hypercube architecture 3

Embedding triple-modular redundancy into a hypercube archite...

引用

3rd Conference on Hypercube Concurrent Computers and Applications, C3P 1988

作者： Kiskis, Daniel L. Shin, Kang G. Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0897912780

This paper describes an embedding of Triple Modular Redundancy (TMR) into a binary hypercube. The goal is to improve fault tolerance by masking any single-point faults. Each module of an application task is triplicated and executed in parallel on three nodes of a 2-dimensional subcube (Q2) of the hypercube. Each of these nodes also executes a voter process. The remaining node is used for message passing only. All outputs from the triplicated modules are voted on, and the voting results are transmitted to the appropriate destination. Thus, all interunit messages are also triplicated. We propose an embedding of TMR into a hypercube which can be implemented in a manner transparent to the application program. Subcubes are allocated so that the address space for the TMR units is also a hypercube. Hence, the subcube allocation and intermodule communication schemes are defined to be analogous to the schemes used in the nonre-dundant system. The embedded system is proven to mask all single-point faults.

关键词： Message passing

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