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Challenges for software engineering in Automation

Journal of software engineering and Applications 2014年第5期7卷 440-451页

作者： Birgit Vogel-Heuser Christian Diedrich Alexander Fay Sabine Jeschke Stefan Kowalewski Martin Wollschlaeger Peter Gohner Institute of Automation and Information Systems Technische Universitat MünchenMünchenGermany Institute for Automation and Communication Otto von Guericke University MagdeburgMagdeburgGermany Institute of Automation Technology Helmut-Schmidt-UniversityHamburgGermany Institute of Information Management in Mechanical Engineering RWTH Aachen UniversityAachenGermany Computer Science 11—Embedded Software Laboratory RWTH Aachen UniversityAachenGermany Institute for Applied Computer Science Dresden University of TechnologyDresdenGermany Institute of Industrial Automation and Software Engineering University of StuttgartStuttgartGermany

This paper gives an introduction to the essential challenges of software engineering and requirements that software has to fulfill in the domain of automation. Besides, the functional characteristics, specific constraints and circumstances are considered for deriving requirements concerning usability, the technical process, the automation functions, used platform and the well-established models, which are described in detail. On the other hand, challenges result from the circumstances at different points in the single phases of the life cycle of the automated system. The requirements for life-cycle-management, tools and the changeability during runtime are described in detail.

关键词： Automation software engineering Models Tools

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Planning in Real-Time Domains with Timed CTL Goals via Symbolic Model Checking

Planning in Real-Time Domains with Timed CTL Goals via Symbo...

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Theoretical Aspects of software engineering (TASE)

作者： Daniel Stöhr Sabine Glesner Software Engineering for Embedded Systems Technical University of Berlin Germany

Current methods for planning in real-time environments only consider planning goals with a restricted expressiveness, even those using the temporal logic Timed CTL (TCTL). These approaches support TCTL subsets expressing rather simple reachability goals and safety properties, but do not allow the arbitrary nesting and conjunction of TCTL formulas. However, this is a serious drawback in many practical applications. An example are medical systems that have to repeat an action infinitely often within given time bounds. To close this gap, we provide an algorithm for planning with these goals by adapting concepts from symbolic model checking. Hence, we can automatically generate plans fulfilling more complex tasks within a real-time context, while improving safety and efficiency by using formally founded model checking methods.

关键词： Planning Automata Clocks Semantics Safety Model checking Aerospace electronics

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Verifying the Accuracy of Automation Tools for the Measurement of software with COSMIC -- ISO 19761 Including an AUTOSAR-Based Example and a Case Study

Verifying the Accuracy of Automation Tools for the Measureme...

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Joint Conference of the Int'l Workshop on and International Conference on software Process and Product Measurement software Measurement

作者： Hassan Soubra Alain Abran Amar Ramdane-Cherif Embedded Systems Team Ecole Supérieure des Techniques Aéronautiques et de Construction Automobile -ESTACA Laval France Department of Software Engineering and IT Ecole de technologie supérieure - ETS - Université du Québec Montréal Canada LISV - Laboratoire d'Ingénierie des Systèmes de Versailles UVSQ Vélizy France

Automating functional size measurement (FSM) is important for organizations needing to measure a large number of projects within a short timeframe, provided, of course, that the results automatically generated are accurate, particularly when such measurement is based on an international measurement standard. A literature review has shown that very little work has been conducted on verifying measurement results produced by FSM automation. This paper presents a verification protocol designed to provide evidence of the accuracy of an automated FSM tool using the COSMIC ISO 19761 measurement standard. Also included are: an example of its use for the verification of an AUTOSAR-based FSM automation prototype tool developed at ESTACA, and a case study on the application of the proposed verification protocol on another prototype tool developed at Renault S.A.

关键词： Automation software Protocols Size measurement software measurement Unified modeling language Accuracy

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Intelligent prediction of execution times

Intelligent prediction of execution times

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International Conference on Informatics & Applications (ICIA)

作者： Dirk Tetzlaff Sabine Glesner Chair Software Engineering for Embedded Systems Technische Universität Berlin

ISBN: (纸本)9781467352543

It is a major challenge in software engineering to statically analyze in advance the expectable run-time behavior of applications. The most needed information is the expected execution time of a function to determine its computational cost. In this paper, we present a sophisticated approach that solves this problem by utilizing Machine Learning (ML) techniques based on regression modeling to automatically derive precise predictions for this information. This enables to focus optimization efforts on the parts that are relevant for the resulting performance and to predict execution times of functions on different processing elements of a heterogeneous architecture. Among others, our approach eliminates the need for manual annotations of run-time information, which automates and facilitates the development of complex software, thus improving the software engineering process. For our experiments that demonstrate the accuracy of our approach, we have used a considerable number of programs from various benchmark suites which encompass different realworld application domains. This shows on the one hand the general applicability and on the other hand the high scalability of our ML techniques.

关键词： Benchmark testing Prediction algorithms Predictive models Vectors Training Support vector machines Feature extraction

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Evaluation of the Task Communication Performance in Wireless Sensor Networks: A Queue Theory Approach

Evaluation of the Task Communication Performance in Wireless...

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IEEE/ACM Int'l Conference on & Int'l Conference on Cyber, Physical and Social Computing (CPSCom) Green Computing and Communications (GreenCom)

作者： Wang Jie Kuan-jiu Zhou Kai Cui Xiang-jie Kong Guang Yang Department of Embedded Systems Engineering Software School of Dalian University of Technology Dalian China

In this paper, a communication task scheduling evaluation model based on the queue model is proposed to analyze the wireless sensor performance parameters. The typical communication task scheduling which deals with all communication tasks scheduling requests and makes actions or responses. A task scheduling-preemptive-priority model is proposed to simulate and analyze typical wireless sensor network using matrix-geometric theory. And then, several merits of the communication task schedule are obtained, including the communication task loss rate, the average response time and the wireless sensor occupancy rate. At last, experiments are conducted to show the performance of our scheme. Simulation results manifest that when sensor usage rate up to 97%, our scheme is feasible for wireless sensor networks.

关键词： Wireless sensor networks Wireless communication Scheduling Queueing analysis Steady-state Time factors Analytical models

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A HW/SW Co-verification framework for systemc

A HW/SW Co-verification framework for systemc

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作者： Herber, Paula Glesner, Sabine International Computer Science Institute 1947 Center Street Berkeley CA 94704 United States Software Engineering for Embedded Systems Group Technical University of Berlin Ernst-Reuter-Platz 7 10587 Berlin Germany

SystemC is widely used for modeling and simulation in hardware/software co-design. However, existing verification techniques are mostly ad-hoc and non-systematic. In this article, we present a systematic, comprehensive, and formally founded co-verification framework for digitalHW/SW systems that are modeled in SystemC. The framework is based on a formal semantics of SystemC and uses a combination of model checking and testing, whereby testing includes both the automated generation of timed inputs and automated conformance evaluation. We demonstrate its performance and its error detecting capability with two case studies, namely a packet switch and an anti-slip regulation and anti-lock braking system. © 2013 ACM.

关键词： Semantics

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Process and tool support for design patterns with safety requirements 13

Process and tool support for design patterns with safety req...

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Proceedings of the 18th European Conference on Pattern Languages of Program

作者： Ansgar Radermacher Brahim Hamid Manel Fredj Jean-Louis Profizi CEA LIST Laboratory of Model driven engineering for embedded systems University of Toulouse Critical Embedded Software Business Unit France ALSTOM Transport Information Solutions France

ISBN: (纸本)9781450334655

The requirement for higher Security and Dependability (S&D) of systems is continuously increasing, even in domains tradi-tionally not deeply involved in such issues. Nowadays, many practitioners express their worries about current S&D software engineering practices. New recommendations should be considered to ground this discipline on two pillars: solid theory and proven principles. We took the second pillar towards software engineering for embedded system applications, focusing on the problem of integrating S&D by design to foster reuse. In this paper, we propose to combine design patterns and Model Driven engineering (MDE) techniques for building component-based applications with safety requirements. The resulting modeling framework serves primarily to capture the basic concepts for specifying safety-oriented design patterns, building an S&D pattern system, and maintain safety properties, with existing modeling artifacts, during the engineering process based on the S&D pattern system. As a proof of concept, we are evaluating the feasibility of the framework through the example of the MooN pattern system for building systems having safety requirements: Communication Based Train Control (CBTC).

关键词： safety model driven engineering traceability component design patterns

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A Concept for Securing Cyber-Physical systems with Organic Computing Techniques

A Concept for Securing Cyber-Physical Systems with Organic C...

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26th International Conference on Architecture of Computing systems 2013

作者： Joerg Haehner Stefan Rudolph Sven Tomforde Dominik Fisch Bernhard Sick Nils Kopal Arno Wacker Organic Computing University of Augsburg Intelligent Embedded Systems University of Kassel Software Engineering for Ubiquitous Computing Applications University of Kassel

Cyber-Physical systems (CPS) are a logical step towards integrating classical IT systems further into physical or virtual surroundings. In consequence this means that CPS will be targets for new security threats, e.g. by manipulating the system both at the IT system level and within its surroundings. In this paper, we first discuss these new types of security threats before suggesting a novel system architecture that extends ideas from the domain of Organic Computing. Finally, we present a research agenda towards building future secure CPS.

关键词： Computer security Computer architecture Information technology Intelligent sensors Human factors Sensor systems

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Preprocessing Technique for Accelerating Reconfiguration of Degradable VLSI Arrays

Preprocessing Technique for Accelerating Reconfiguration of ...

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IEEE International Symposium on Circuits and systems

作者： Yuanbo Zhu Jigang Wu Siew-Kei Lam Thambipillai Srikanthan School of Computer Science and Software Engineering Tianjin Polytechnic University 300387 Tianjin China Centre for High Performance Embedded Systems Nanyang Technological University 639789 Singapore

ISBN: (纸本)9781467357609

This paper presents a heuristic approach to accelerate the reconfiguration of two-dimensional degradable VLSI arrays linked by 4-port switches in presence of faulty processing elements (PEs). In particular, we proposed a technique to preprocess the host array by 1) identifying fault-free PEs that cannot form the target array due to their proximity to faulty PEs, and 2) labeling these fault-free PEs as faults. The proposed preprocessing method minimizes the number of PEs that will be considered for reconfiguration, thus accelerating the reconfiguration process. Simulation results show that the runtime of two well-known algorithms are significantly reduced by employing the preprocessing technique. In addition, we demonstrate the scalability of the proposed technique by showing that the runtime reduction rate increases with increasing fault density.

关键词： Preprocessing Technique Accelerating Reconfiguration Degradable VLSI Arrays Reconfiguration Pretreatment Technology acceleration arrays Very large scale integration fault density Runtime fault-free

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Comparative evaluation of an error checking approach for MPSoC

International Journal of Multimedia and Ubiquitous Engineeri...

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International Journal of Multimedia and Ubiquitous engineering 2013年第5期8卷 145-158页

作者： Liu, Tang Qin, Huang-Zhang Bin, Hou-Yi Cai, Fang-Feng Bing, Zhang-Hui Embedded Software and Systems Institutes Beijing University of Technology China Department of Physics and Electronics Engineering Guangxi Teachers Education University Nanning 530024 China Department of computer science and Electronics Engineering GuiLin University of Electronic Technology GuiLin 541004 China

This paper proposes a hardware error checking approach (CCRC) by using redundancy core for multiprocessor system-on-chip (MPSoC) and describes several main error detection methods based on software-Implemented Hardware Fault Tolerance (SHIF) idea proposed in literatures. The CCRC approach insert some error detection code in high level code, detect the existing of redundancy core in MPSoC, then complete the calculation of detection code in redundancy core. The author compares the CCRC approach with several main error detection methods on error detection capabilities, area, memory and performance overheads in an experiment platform. The result of comparative evaluation shows that the CCRC approach is effective for MPSoC, taking some advantages in versatility and lower cost. © 2013 SERSC.

关键词： Redundancy

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