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CyberROAD: A cybersecurity risk assessment ontology for automotive domain aligned with ISO/SAE 21434:2021

JOURNAL OF INFORMATION SECURITY AND APPLICATIONS 2025年 90卷

作者： Khalil, Karim Gehrmann, Christian Vogel, Guenther Lund Univ EIT Elect & Informat Technol Ole Romers Vag 3 SE-22100 Lund Skane Sweden Robert Bosch GmbH Vehicle Mot Syst Engn Platform Syst & Software Architecture Platform Safety & Secur Asperger Str 24 D-74321 Stuttgart Germany

The automotive domain is becoming increasingly complex through the integration of new technologies. As a result, cybersecurity is recognized as a pressing issue. This study focuses on the ISO/SAE 21434:2021 standard for road vehicles cybersecurity engineering, evaluating the effectiveness of the standard's risk assessment approach. The standard suggests a set of assessment steps, and previous research has shown that practitioners often face challenges during assessment execution. The absence of clear, structured guidelines within the standard leads to different interpretations, resulting in inconsistent assessment approaches. This inconsistency makes it difficult to compare and measure the quality of the assessments. Our study uses design science methodology to create a new cybersecurity risk assessment ontology in the automotive domain, describing the relationships and interdependencies between cybersecurity risk assessment activities, stakeholders, and work packages. The ontology model is evaluated in a case study at a leading automotive systems supplier to validate the model's suitability for developing a cybersecurity risk assessment method. The findings indicate that the ontology model provides an improved understanding of the underlying risk assessment activities and allows for a structured method for extracting procedural steps according to the standard. This systematic approach increases the cybersecurity risk assessment conformity and the consistency of assessment results. In conclusion, this paper gives valuable insights and actionable recommendations for stakeholders, researchers, and organizations seeking to improve the cybersecurity risk assessment process in the automotive domain.

关键词： Cybersecurity risk assessment Ontology Automotive domain Threat analysis and risk assessment (TARA) Design science research method

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NIC-QF: A design of FPGA based Network Interface Card with Query Filter for big data systems

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2022年 136卷 153-169页

作者： Zhan, Jinyu Jiang, Wei Li, Ying Wu, Junting Zhu, Jianping Yu, Jinghuan Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Tencent Technol Shenzhen Co Ltd Res Dept Architecture & Platform Shenzhen Peoples R China City Univ Hong Kong Dept Comp Sci Hong Kong Peoples R China

This paper presents an approach to accelerate query processing on storage and computing separated big data systems. Different from traditional co-processor methods, we propose an FPGA based Network Interface Card with Query Filter (NIC-QF) to pre-filter data on storage nodes. Without modifying the hardware architecture in storage nodes, the traditional NIC can be easily replaced with our NIC-QF to reduce the workload of computing nodes and the corresponding communication overhead. Integrated with the PCIe core, query filter and NIC communicator, NIC-QF can filter the original data on storage nodes and directly send the filtered data to computing nodes of big data systems to reduce the extra communication overheads inside the storage nodes. The filter units in a query filter perform multiple SQL tasks in parallel, and each filter unit is internally pipelined, which further speeds up data processing. The filter units are designed to support general SQL queries in various data formats including TextFile (a row-based storage format) and RCFile (a column-based storage format). Experiments on the TPC-H benchmark and the Tencent data set demonstrate the superiority of our design, saving up to 87.84% of time overhead compared with the traditional approaches. (C) 2022 Elsevier B.V. All rights reserved.

关键词： Big data systems Storage and computing separated architecture Network Interface Card FPGA Acceleration Query filter

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Accelerating Queries of Big Data Systems by Storage-Side CPU-FPGA Co-Design

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2022年第7期41卷 2128-2141页

作者： Zhan, Jinyu Jiang, Wei Li, Ying Wu, Junting Zhu, Jianping Yu, Jinghuan Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu 610054 Peoples R China Tencent Technol Shenzhen Co Ltd Res Dept Architecture & Platform Shenzhen 518000 Peoples R China City Univ Hong Kong Dept Comp Sci Hong Kong Peoples R China

As a promising technology of big data systems, storage and computing separated architecture has attracted increasing attention of famous companies, such as Tencent, IBM, Facebook, and Microsoft. Under this new architecture, conventional query engines like Hive and Presto choose all the original data from storage nodes and send them to computing nodes to be filtered, causing high data transmission overhead and great I/O bandwidth fluctuation. To address this problem, we design a novel data processing framework to prefilter data on storage side, and then propose a CPU-FPGA (field-programmable gate array) co-design to accelerate the queries with the purpose of reducing the communication overheads and the workloads of computing nodes. To obtain the optimal efficiency of CPU-FPGA co-processing, a workload-aware task scheduler is designed to allocate query tasks to CPU or FPGA according to the estimation of the filtering data size and processing time of query tasks. A data projection scheme is designed to support data in RCFile format which is widely used in modern systems, such as Tencent and Facebook applications. To make full use of the high parallelism of FPGA, we formulate the SQL conditions of combined predicates into Boolean parameters, and design two filtering schemes on FPGA (i.e., parallel sequential filter for fix-length data type and parallel pipeline filter for variable-length data type). Experiments on the TPC-H benchmark and Tencent data set demonstrate the efficiency of our approach, which can save up to 72.28% and 80.16% of time overheads compared with Presto and Hive, respectively.

关键词： Field programmable gate arrays Computer architecture Big Data Task analysis Data processing software Information filters Big data systems co-design field-programmable gate array (FPGA) query filter SQL

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FPGA Based Co-design of Storage-side Query Filter for Big Data Systems 33

FPGA Based Co-design of Storage-side Query Filter for Big Da...

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33rd IEEE International System on Chip Conference (IEEE SOCC)

作者： Zhan, Jinyu Li, Ying Jiang, Wei Zhu, Jianping Univ Elect Sci & Technol China Sch Informat & Software Chengdu Peoples R China Tencent Technol Shenzhen Co Ltd Res Dept Architecture & Platform Shenzhen Peoples R China

ISBN: (纸本)9781728187464

In this paper we are interested in accelerating the processing of big data systems. We consider the architecture of storage and computing separated Big Data systems, and approach to improve the data query efficiency in the storage side. We propose an Field Programmable Gate Array (FPGA) based co-design of query filter on storage nodes to reduce the workloads of computing nodes and the communication overheads between them. The co-design of query filter is composed of software layer and FPGA layer. In software layer, we use the pointers to project the data in the RCFile format to reduce data transmission, and then formulate the combined predicate of SQL conditions into parameters. In FPGA layer, we design two filtering schemes on FPGA for data in RCFile format, i.e. parallel sequential filter and parallel pipeline filter, by which we can achieve that different columns and SQL queries are completely parallel. Based on TPC-H benchmark and Tencent data set, we conduct extensive experiments to evaluate our design, which can save averagely 76.2% of time overhead compared with Presto and 96.86% of time overhead compared with Hive.

关键词： big data query filter SQL FPGA co-design

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S-WAL: Fast and Efficient Write-Ahead Logging for Mobile Devices

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2018年第3期64卷 319-327页

作者： Kang, Dong Hyun Kang, Woonhak Eom, Young Ik Sungkyunkwan Univ Coll Software Suwon 2066 South Korea eBay Core Platform & Infrastruct Architecture San Jose CA USA

A crash-consistency mechanism of database application (hereinafter DBMS for short) imposes an enormous burden on the journaling process of the file system (e.g., JBD2) in that it employs regular files on the file system to persistently preserve the application's journal data with synchronous system calls. Unfortunately, much of the previous research is impractical in real-world scenarios because they require changing a lot of source lines of code in multiple software layers of the software stack or using special hardware (e.g., the transactional flash storage or NVM technologies). In this paper, we propose a new journal mode of DBMS, called S-WAL, which compresses the raw data journaled by the database to alleviate both the redundant journaling operations and harmful write amplification. We believe that S-WAL is a practical way to support application-level crash consistency on the existing mobile devices because only a few lines of DBMS code need to be changed, without the need to employ special hardware. We demonstrate the effectiveness of S-WAL by running four popular mobile applications on the latest smartphone. Our evaluation results show that S-WAL considerably outperforms existing journal modes of DBMS in all cases. In the best case, S-WAL reduces the elapsed time by up to 7.5x more than the PERSIST mode and by up to 51% more than the traditional WAL mode.

关键词： Mobile applications write-ahead logging database systems

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Future Automotive Archite cture and the Impact of IT Trends

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IEEE software 2017年第3期34卷 27-32页

作者： Traub, Matthias Maier, Alexander Barbehon, Kai L. BMW E E Architecture Next Munich Germany BMW E E Architecture Platform Munich Germany BMW E E Architecture Dept Munich Germany BMW E E & Software Architecture Platform Management Munich Germany

architectures for automotive electronics are quickly changing. Energy efficiency is evolving the classic powertrain toward high-voltage hybrid and electric engines. Autonomous driving demands multisensor fusion away from functionally isolated control units. Connectivity and infotainment have transformed the car into a distributed IT system with cloud access;over-the-air functional upgrades;and high-bandwidth access to map services, media content, other vehicles, and the surrounding infrastructure. Here, Matthias Traub, Alexander Maier, and Kai Barbehn of BMW outline the evolution of automotive electronics and IT. I look forward to hearing from both readers and prospective column authors.

关键词： Automotive Electric Vehicles Automotive Electronics Automotive Engineering Cloud Computing Energy Conservation Hybrid Electric Vehicles Power Transmission Mechanical Sensor Fusion Automotive architecture Automotive Electronics Automotive Domain Automotive Industry Energy Efficiency High Voltage Hybrid Engines Electric Engines Powertrain Multisensor Fusion Functionally Isolated Control Units Distributed IT System Cloud Access Over The Air Functional Upgrades Media Content IT Transfer Computer architecture Automotive Engineering Service Oriented architecture Sensors Servers E E architecture Electrical And Electronic architecture Automotive software EC Us Electronic Control Units SOA Service Oriented architecture Consumer Electronics IT software Engineering software Development

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Ranking software Components Using a Modified PageRank Algorithm Including Safety Aspects 14

Ranking Software Components Using a Modified PageRank Algori...

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International Conference on Embedded Computer Systems - architectures, Modeling, and Simulation (SAMOS)

作者： Reinhardt, Dominik BMW Grp Software Architecture & Platform Software Munich Germany

ISBN: (纸本)9781479937707

Automotive software is increasing rapidly in its size, amount or complexity and the demand for calculation power rises. According ISO26262, additional non-functional requirements for safety-relevant applications must be considered. Therefore, analyzing software networks is necessary to identify problems within an early development state. For future multicore systems, complex software structures probably impede a safe segregation of software components between cores. In this paper, we want to use social network measurement methods to analyze automotive software architectures. Here, the interconnection of single software components and their influence within the network is focused. We use a modification of Google's PageRank algorithm, where websites partly inherit the rank of their interlinked neighboring websites, and transfer these techniques to automotive needs. For our evaluation, we use data structures of an exemplary electronic control unit of BMW.

关键词： Websites

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Ranking software components using a modified PageRank algorithm including safety aspects

Ranking software components using a modified PageRank algori...

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International Conference on Embedded Computer Systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Dominik Reinhardt Software-Architecture and Platform Software BMW Group Munich Germany

关键词： software Safety Automotive engineering software algorithms Multicore processing Computational modeling Vectors

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Clause Anaphora Resolution for Japanese Demonstrative Determiner based on Semantic Similarity between Different Part-of-Speech

Clause Anaphora Resolution for Japanese Demonstrative Determ...

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IEEE International Conference on Systems, Man, and Cybernetics (SMC)

作者： Ikegami, Yukino Damiani, Ernesto Urano, Akihiro Tsuruta, Setsuo Tokyo Denki Univ Sch Informat Environm Chiba Japan Univ degli Studi Milano Serv Oriented Software Architecture Res Lab Dipartimento Tecnol Informazione Milan Italy Hitachi Ltd IT Platform R&D Management Div Kanagawa Japan

ISBN: (纸本)9781479906529

An anaphora is a type of expression whose reference depends upon another referential element. In order to become aware of situations or human intentions by natural language understanding, it is important to estimate correctly what anaphoric expressions indicate. In particular, an anaphora resolution for Japanese demonstrative determiners is critical to be aware of situation, context or a causal relationship in dialogue. Ontology-based similarity has been proposed as a way to identify referential elements;however, a method using ontology alone cannot resolve all anaphoric relations. This paper proposes an anaphora analysis method that uses semantic similarity between different part-of-speech and conceptual dependency structure. This method specializes in resolving clause anaphoric. The evaluation of this method showed 100% accuracy for resolving Japanese demonstrative determiner in counseling dialogue.

关键词： anaphora resolution clause anaphoric demonstrative determiner ontology

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A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2013年第7期48卷 1669-1679页

作者： Carballido, Jorge Hermosillo, Jorge Veloz, Arturo Arditti, David Del Rio, Alberto Borrayo, Edgar Guzman, Manuel E. Lakdawala, Hasnain Verhelst, Marian Intel Labs Syst Integrat & Adapt Grp Guadalajara 45600 Jalisco Mexico Intel Architecture Grp Platform Validat & Engn Grp Guadalajara 45600 Jalisco Mexico Software & Serv Grp Processor BT Validat & Tools Grp Guadalajara 45600 Jalisco Mexico Qualcomm Technol Inc San Diego CA 92121 USA Katholieke Univ Leuven ESAT Microelect & Sensors Div MICAS B-3001 Louvain Belgium

This paper presents a flexible and portable digital framework for Built-in Self-Test (BIST) and calibration of RF/analog circuitry. Novel to the proposed testing framework, is a reusable, flexible, drop-in IP core, composed of a centralized custom processing engine with data path, memory architecture and instruction set optimized for efficient execution of compute intensive test and calibration algorithms. The innovative BIST engine is complemented with a calibration and test sequencing methodology exploiting the embedded test hardware, to dynamically correct for transceiver imbalances and non-idealities, as well as to estimate performance parameters such as Error Vector Magnitude (EVM). The engine has been integrated with a WiFi transceiver in a 32 nm SoC test chip to demonstrate the functionality of this framework. This implementation covers an area of 0.63 mm(2) and provides similar performance (e.g., improvements up to 10 dB in EVM for Rx IQ imbalance compensation) to off-chip testing without relying on expensive equipment.

关键词： Calibration testing radio transceiver IQ imbalance PAPD SoC RF manufacturing

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