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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhang, Yuxuan Zhao, Yutong Lan, Jingchao Ye, Fan Xie, Yufeng Ren, Junyan State Key Lab. of ASIC & System Fudan University Shanghai China School of Microelectronics Fudan University

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper presents a 6-bit 800MS/s successive approximation register (SAR) analog-to digital converter (ADC) in 28nm CMOS with grouped digital-to-analog converter (DAC) capacitor array. High-speed operation is achieved by improving the control logic and using custom-designed unit capacitor of comb structure. At 800MS/s sampling rate with Nyquist input, the post simulated SNDR and SFDR are 37.68dB and 50.1dB respectively, and the ADC core consumes 1.82mW from 1V supply, achieving 36.5fJ/conversion-step. © 2022 IEEE.

关键词： Digital to analog conversion

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High Efficient Automatic Power/Ground Layout Routing Algorithm for Analog ICS

High Efficient Automatic Power/Ground Layout Routing Algorit...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Zuo, Jiaxin. Li, Fei. Wan, Jing. Fudan University State Key Lab of Asic and System School of Information Science and Engineering Shanghai China Suzhou Foohu Technology Co. Ltd. China

ISBN: (纸本)9798350311006

In this work, we explored an efficient automatic layout routing algorithm for connecting the power and ground pins in analog integrated circuits. A rectilinear minimal spanning tree (RMST) algorithm for two sets of pins is developed, in which minimal spanning tree is used to form the initial connections between pins. The obstacle-avoiding maze routing algorithm is used to break and reconnect the power and ground nets to avoid any short circuit. The genetic algorithm (GA) is further introduced to optimize the total connection wirelength. We also expanding the wire width to avoid electromigration and IR-drop. © 2023 IEEE.

关键词： Routing algorithms

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High-Dimensional Analog Circuit Sizing via Bayesian Optimization in the Variational Autoencoder Enhanced Latent Space

High-Dimensional Analog Circuit Sizing via Bayesian Optimiza...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Wangzhen Li Zhaori Bi Xuan Zeng Microelectronics Department State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

High-dimensional analog circuit sizing with machine learning-based surrogate models suffers from the high sampling cost of evaluating expensive black-box objective functions in huge design spaces. This work addresses the sampling efficiency challenge by elaborately reducing the dimensionality of the input spaces, enabling efficient optimization for automated analog circuit sizing. We propose a latent space optimization method that includes an iteratively updated generative model based on a variational autoencoder to embed the solution manifold of analog circuits to a low-dimensional and continuous space, where the latent variables are optimized using Bayesian optimization. The effectiveness of the proposed method has been verified on two real-world analog circuits with 18 and 59 design variables. In comparison with BO in the original high-d spaces or latent low-d spaces assisted by other embedding strategies, the proposed method achieves 23%~73% improvements in optimization per-formance within the same runtime limitations. We also conduct a technology migration experiment using the pre-trained variational autoencoder model, which demonstrates the necessity of pre-training and the scalability of the proposed method.

关键词： Manifolds Runtime Design automation Costs Scalability Optimization methods Closed box

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SDformer: Efficient End-to-End Transformer for Depth Completion

arXiv

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arXiv 2024年

作者： Qian, Jian Sun, Miao Lee, Ashley Li, Jie Zhuo, Shenglong Chiang, Patrick Yin State Key Lab of ASIC & System Fudan University Shanghai China PhotonIC Technologies

Depth completion aims to predict dense depth maps with sparse depth measurements from a depth sensor. Currently, Convolutional Neural Network (CNN) based models are the most popular methods applied to depth completion tasks. However, despite the excellent high-end performance, they suffer from a limited representation area. To overcome the drawbacks of CNNs, a more effective and powerful method has been presented: the Transformer, which is an adaptive self-attention setting sequence-to-sequence model. While the standard Transformer quadratically increases the computational cost from the key-query dot-product of input resolution which improperly employs depth completion tasks. In this work, we propose a different window-based Transformer architecture for depth completion tasks named Sparse-to-Dense Transformer (SDformer). The network consists of an input module for the depth map and RGB image features extraction and concatenation, a U-shaped encoder-decoder Transformer for extracting deep features, and a refinement module. Specifically, we first concatenate the depth map features with the RGB image features through the input model. Then, instead of calculating self-attention with the whole feature maps, we apply different window sizes to extract the long-range depth dependencies. Finally, we refine the predicted features from the input module and the U-shaped encoder-decoder Transformer module to get the enriching depth features and employ a convolution layer to obtain the dense depth map. In practice, the SDformer obtains state-of-the-art results against the CNN-based depth completion models with lower computing loads and parameters on the NYU Depth V2 and KITTI DC datasets. Our codes are available at https://***/JamesQian11/SDformerfor-Depth-Completion Copyright © 2024, The Authors. All rights reserved.

关键词： Convolution

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PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design

PRAD: A Bayesian Optimization-based DSE Framework for Parame...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Bingbing Peng Shaoyang Sun Yuan Dai Jingyuan Li Yunhui Qiu Kaihang Wang Wenbo Yin Lingli Wang State Key Lab of ASIC and System Fudan University China

Coarse-Grained Reconfigurable Architecture (CGRA) is a domain-specific reconfigurable architecture. Generally, the CGRA architecture consists of IO, memory, coarse-grained processing element (PE), and interconnect. Usually, ALU in PE contains a relatively complete set of operations and most of the interconnects adopt neighbor-to-neighbor (N2N) [1], switch-based [2], and combination of the connection box and switch box (CB-SB) patterns [3]. However, the complex operation sets and switch-based/CB-SB fully-connected interconnects provide sufficient reconfigurability at the cost of resource overhead. Thus, it is important to build a parameterized architecture of CGRA to achieve a balance among hardware overhead, flexibility and performance through automatic design space exploration (DSE).

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HierSyn: Fast Synthesis for Large Hierarchical Designs 15

HierSyn: Fast Synthesis for Large Hierarchical Designs

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15th IEEE International Conference on asic, asicON 2023

作者： Zhang, Yishan Zhang, Zhiyong Wu, Chang Fudan University State-Key Lab of ASIC and System School of Microelectronics Shanghai200433 China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai200433 China

ISBN: (纸本)9798350312980

As design goes into multi-billion transistors, the synthesis runtime becomes an important issue, particularly for design verification and prototyping, as one may run the synthesis many times with design change. Module-by-module synthesis with multi-threading is a natural solution for fast synthesis, however, at the cost of quality of results (QoR) degradation. Besides, multi-thread speedup may not be so good due to very uneven sizes of the modules. In this paper, we propose a design hierarchy restructuring based multi-thread synthesis algorithm for large-scale designs. Small module flattening and large module partitioning are used to create moderate size design modules. Our experimental results show that our algorithm can produce results within 3% area increase and 21.3x speedup over the flat synthesis flow. © 2023 IEEE.

关键词： Logic Optimization Logic Synthesis Multi-thread

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Hierarchical Optimization Algorithm for the Automatic Design of Analog Integrated Circuit

Hierarchical Optimization Algorithm for the Automatic Design...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yu Zong Jing Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China

ISBN: (数字)9798331513351

ISBN: (纸本)9798331513368

In this work, we have explored the use of hierarchical optimization technique to automatically design low dropout regulator. When we use genetic algorithm for multi-objective optimization, the increase of design variables will greatly increase the difficulty of optimization. Therefore, we divide the whole circuit into different levels and only upload the sub circuits’ combination of design parameters to reduce the design variables and shorten the optimization time. In our work, we have explored the optimization results under different constraints, and compared them with the direct optimization results systematically.

关键词： Regulators Optimization Genetic algorithms Analog integrated circuits

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Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGA

Moth: A Hardware Accelerator for Neural Radiance Field Infer...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Yuanfang Wang Yu Li Haoyang Zhang Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China

Neural Radiance Field (NeRF) is a state-of-the-art algorithm in the field of novel view synthesis and has the potential to be used in AR/VR. However, the inference of NeRF is time-consuming. Motivated by resource-constraint scenarios on the edge and mixed reality devices, our essential idea is to bridge this gap while improving throughput and power consumption. This paper proposes a high-performance FPGA-based accelerator, with a fully-pipelined design tailored for the vanilla NeRF algorithm. We also design a mechanism to monitor the output of the rendering module to reduce operations. Experimental results show that our accelerator achieves 3.63× energy efficiency over implementation on GPU NVIDIA V100, and 1.31× speed up over state-of-the-art asic design if running under the same clock frequency as asic.

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A Decision-Based CORDIC Hardware for Arc Tangent Calculation

A Decision-Based CORDIC Hardware for Arc Tangent Calculation

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International Conference on asic

作者： Haoyu Wu Liyu Lin Haodong Sun Xiaoyang Zeng Yun Chen State Key Lab of ASIC & System Fudan University Shanghai China

The COordinate Rotation DIgital Computer (CORDIC) simplifies the elementary function using bit-shift operation and addition. However, the iteration increases with the accuracy and causes a long latency. In this paper, we propose a decision-based CORDIC hardware for arc tangent calculation, which introduce a comparator to determine the necessity of the rotation in every iteration. By bypassing the redundant processes, the proposed CORDIC achieve a higher accuracy. Besides, the regular structure is also friendly for folding implementation. Experiments show that compare with the conventional CORDIC, the decision-based CORDIC hardware has an improvement of 28.1% in accuracy. Synthesis results in 65nm technology shows that the proposed unfolding hardware consumes an area of 0.774mm 2 and a power of 0.644mW under 65nm technology, which has an improvement of about 13.7% and 3% in comparison with the conventional CORDIC, and the folding structure has an area of 0.164mm 2 and a power of 0.243mW .

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FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks

FET-OPU: A Flexible and Efficient FPGA-Based Overlay Process...

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IEEE International Conference on Computer-Aided Design

作者： Yueyin Bai Hao Zhou Keqing Zhao Hongji Wang Jianli Chen Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China

There are already some works on accelerating transformer networks with field-programmable gate array (FPGA). However, many accelerators focus only on attention computation or suffer from fixed data streams without flexibility. Moreover, their hardware performance is limited without schedule optimization and full use of hardware resources. In this article, we propose a flexible and efficient FPGA-based overlay processor, named FET-OPU. Specifically, we design an overlay architecture for general accelerations of transformer networks. We propose a unique matrix multiplication unit (MMU), which consists of a processing element (PE) array based on modified DSP-packing technology and a FIFO array for data caching and rearrangement. An efficient non-linear function unit (NFU) is also introduced, which can calculate arbitrary single input non-linear functions. We also customize an instruction set for our overlay architecture, dynamically controlling data flows by instructions generated on the software side. In addition, we introduce a two-level compiler and optimize the parallelism and memory allocation schedule. Experimental results show that our FET-OPU achieves 7.33-21.27× speedup and 231× less energy consumption compared with CPU, and 1.56-4.08× latency reduction with 5.85-66.36× less energy consumption compared with GPU. Furthermore, we observe 1.56-8.21× better latency and 5.28-6.24× less energy consumption compared with previously customized FPGA/asic accelerators and can be 2.05× faster than NPE with 5.55× less energy consumption.

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