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2D Ruddlesden-Popper Perovskites/PVDF-TrFE Photodetector for Anti-Interference Vision system Derived from Ferroelectric Polarization Modulation

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ADVANCED FUNCTIONAL MATERIALS 2025年第20期35卷

作者： Zhang, Xinglong Hong, Enliu Tan, Xiaojun Liu, Jie Jiang, Anquan Fang, Xiaosheng Fudan Univ Dept Mat Sci State Key Lab Mol Engn Polymers Shanghai 200433 Peoples R China Shaoxin Lab Shaoxing 312000 Peoples R China Fudan Univ Sch Microelect State Key Lab ASIC&System Shanghai 200433 Peoples R China

2D Ruddlesden-Popper (RP) perovskites have garnered increasing attention for their excellent photoresponse, characterized by high carrier mobility, tunable bandgaps, high optical absorption, and molecular asymmetry. Herein, centimeter scale single crystal 2D hybrid perovskites, BA2PbBr4 (BPB) is synthesized, using quasi-static cooling method and composited with ferroelectric PVDF-TrFE(PT) film to construct a multi-field coupling photodetector (PD) via van der Waals force contact. Ferroelectric tests show that the PT film exhibits a saturated polarization strength of 3.6 mu C cm-2, allowing the ferroelectric localized field to modulate the band structure of PT and enhance the photocurrent. The Heterojunction systems exhibit ultra-high responsivity (15.3 A W-1) and detectivity (1.99 x 1013 Jones) under 390 nm illumination at 3 V bias, with a performance improvement of over 102 times compared to BPB PDs. Furthermore, the hybrid PDs exhibit highly stable I-t curve with a photocurrent retention rate of 97.4%. Leveraging this feature, a large-area imaging device is designed at the centimeter level scale, enabling multifunctional vision applications accurate letter imaging process and anti-interference number detection. The work presents a valuable insight in design of future autonomous driving vision systems.

关键词： 2D Ruddlesden-Popper perovskites ferroelectric photodetector PVDF-TrFE single-crystal

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Automated Design of Complex Analog Circuits with Multiagent Based Reinforcement Learning 23

Automated Design of Complex Analog Circuits with Multiagent ...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Jinxin Zhang Jiarui Bao Zhangcheng Huang Xuan Zeng Ye Lu State Key Lab. of ASIC & System School of Information Science and Technology Frontier Institute of Chip and System State Key Lab. of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798350323481

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It's shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

关键词： complex analog circuits

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Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2025年

作者： Gu, Hao Gu, Jian Peng, keyu Chen, Jianli Yang, Jun Zhu, Ziran Southeast University National ASIC System Engineering Research Center School of Integrated Circuits Nanjing210096 China Fudan University State Key Lab of ASIC and System Shanghai200433 China

Field-programmable gate array (FPGA) macro placement holds a crucial role within the FPGA physical design flow since it substantially influences the subsequent stages of cell placement and routing. With the increasing number of macros and the complex cascade shape and region constraints imposed by modern FPGAs, the routability and macro placement have become much more challenging. In this paper, we propose an effective and efficient routability-driven macro placement algorithm for modern FPGAs with cascade shape and region constraints. To reserve adequate space for cell placement and guarantee routability, we first develop a routability-driven mixed-size analytical global placement that evenly distributes both macros and cells while considering cascade shape and region constraints. Particularly, the proposed global placement engine integrates a well-trained congestion prediction model, targeting benchmarks with high routing congestion to enhance overall routability. Then, we propose an integer linear programming (ILP)-based cascade shape legalization followed by matching-based macro legalization to remove macro overlaps while satisfying the region constraints. Finally, a routability-driven detailed macro placement is proposed to refine the solution. Compared with the winners of the MLCAD 2023 FPGA macro placement contest and state-of-the-art works, experimental results show that our algorithm achieves the best overall score and routability. © 1982-2012 IEEE.

关键词： Electronic design automation

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The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

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A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

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Journal of Semiconductors 2011年第2期32卷 73-78页

作者：袁宇丹李立常虹郭亚炜程旭曾晓洋 State Key Laboratory of ASIC&System Fudan University

A fourth-order switched-capacitor bandpass ∑△ modulator is presented for digital intermediatefrequency （IF） receivers. The circuit operates at a sampling frequency of 100 MHz. The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators. The modulator is implemented in a 0.13-μm standard CMOS process. The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB, respectively, over a bandwidth of 200 kHz centered at 25 MHz, and the power dissipation is 8.2 mW at a 1.2 V supply.

关键词： analog-to-digital converter bandpass sigma-delta modulator resonator IF receiver

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Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints 23

Toward Optimal Filler Cell Insertion with Complex Implant La...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Peng Zou Guohao Chen Zhifeng Lin Jun Yu Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China

ISBN: (纸本)9798350323481

Modern circuits often contain standard cells of different threshold voltages (multi-VTs) to achieve a better trade-off between timing and power consumption. Due to the heterogeneous cell structures, the multi-VTs cells impose various implant layer constraints, further complicating the already time-consuming filler cell insertion process. In this paper, we present a fast and near-optimal algorithm to solve the filler insertion problem with complex implant layer rules and minimum filler width constraints. We first propose an inference-driven detecting algorithm to identify each design rule violation accurately. Then, a dynamic-programming-based insertion method is developed to reduce the implant layer violations. Finally, we design a contour-driven violation refinement strategy to further improve manufacturability. Experimental results show that our algorithm can reduce the number of violations significantly compared with state-of-the-art works. Besides, with our identifier in the legalization stage, we can avoid conflicts in advance and solve almost all violations after filler insertion in industrial cases.

关键词： filler insertion

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A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

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Journal of Semiconductors 2013年第3期34卷 81-85页

作者：江晨黄煜梅洪志良 State Key Laboratory of ASIC&System Fudan University

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is *** enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of *** GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^*** to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 *** a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

关键词： time-to-digital converter gated ring oscillator effective resolution all-digital phase locked loop

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A high dynamic range linear RF power detector with a preceding LNA

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Journal of Semiconductors 2012年第1期33卷 107-113页

作者： Dai Yingbo Han Kefeng Yan Na Tan Xi State Key Laboratory of ASIC&System Fudan University.Shanghai 201203 China State Key Laboratory of ASIC&System Fudan University Shanghai 201203China

A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band. In order to increase sensitivity, a low noise amplifier （LNA） is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area, but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So a DC offset cancelling （DCOC） technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in 4-1 dB at 900 MHz/2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27×0.67 mm2.

关键词： logarithmic amplifier successive detection low noise amplifier （LNA） DC offset cancelling （DCOC） power detector （PD）

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Analysis and implementation of an improved recycling folded cascode amplifier

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Journal of Semiconductors 2012年第2期33卷 64-70页

作者： Li Yilei Han Kefeng Yan Na Tan Xi Min Hao ASIC&System State Key Laboratory Fudan UniversityShanghai 201203China

A generally improved recycling folded cascode（IRFC） is analyzed and *** and comparisons among the IRFC,the original recycling folded cascode（RFC） and the conventional folded cascode （FC） are made,and it is shown that with the flexible structure of IRFC,significant enhancement in transconductance, slew rate and noise can be *** amplifiers were fabricated in 0.13μm *** shows that IRFC has 3×enhancement in gain-bandwidth and slew rate over conventional FC,and the enhancement is 1.5x when compared with the RFC.

关键词： CMOS operational amplifiers transconductance noise low-power circuits

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Analysis and implementation of derivative superposition for a power amplifier driver

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Journal of Semiconductors 2012年第4期33卷 81-88页

作者：李一雷韩科峰闫娜谈熙闵昊 ASIC&System State Key Laboratory Fudan UniversityShanghai 201203China

A new expression is proposed to analyze the linearization effectiveness of derivative superposition （DS） with large and small signal inputs, and different optimization methods of DS are found for different input magni tudes. A power amplifier driver （PAD） with largesignal optimized DS was implemented in 0.13/,m technology within a reconfigurable RF transmitter. The PAD is compatible with the GSM band at 900 MHz and the WCDMA band at 1.95 GHz, and it has a gain range of 44 dB with a step of 2 dB. Measurement results show that the over all OIP3 of the transmitter is better than 19 dBm, and the output referred 1dB compression point is better than 7.5 dBm.

关键词： amplifier linearity derivative superposition

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