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A 1500 mA,10 MHz on-time controlled buck converter with ripple compensation and efficiency optimization

Journal of Semiconductors 2012年第1期33卷 86-92页

作者： Yu Jiale LüDanzhu Hong Zhiliang State Key Laboratory of ASIC&System Fudan University Shanghai 201203China

A 1500 mA,10 MHz self-adaptive on-time （SOT） controlled buck DC-DC converter is presented. Both a low-cost ripple compensation scheme （RCS） and a self-adaptive on-time generator （SAOTG） are proposed to solve the system stability and frequency variation problem. Meanwhile a self-adaptive power transistor sizing （SAPTS） technique is used to optimize the efficiency especially with a heavy load. The circuit is implemented in a 2P4M 0.35μm CMOS process. A small external inductor of 0.47 μH and a capacitor of 4.7 μF are used to lower the cost of the converter and keep the output ripple to less than 10 mV. The measurement results show that the overshoot of the load transient response is 8 mV @ 200 mA step and the dynamic voltage scaling （DVS） performance is a rise of 16/zs/V and a fall of 20 μs/V. With a SAPTS technique and PFM control, the efficiency is maintained at more than 81% for a load range of 20 to 1500 mA and the peak efficiency reaches 88.43%.

关键词： buck converter high frequency large current load efficiency on-time control

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Peripheral Ferroelectric Domain Switching and Polarization Fatigue in Nonvolatile Memory Elements of Continuous Pt/SrBi_(2)Ta_(2)O_(9)/Pt Thin-Film Capacitors

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Chinese Physics Letters 2011年第7期28卷 275-277页

作者： CHEN Min-Chuan JIANG An-Quan State Key Laboratory of ASIC&System Department of MicroelectronicsFudan UniversityShanghai 200433

We verify the domain sideway motion around the peripheral regions of the crossed capacitors of top and bottom electrode bars without electrode *** avoid the crosstalk problem between adjacent memory cells,the safe distance between adjacent elements of Pt/SrBi_(2)Ta_(2)O_(9)/Pt thin−film capacitors is estimated to be 0.156µ***,the fatigue of Pt/SrBi_(2)Ta_(2)O_(9)/Pt thin-film capacitors is independent of the individual memory size due to the absence of etching damage.

关键词： electrode volatile film

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Erasable Ferroelectric Domain Wall Diodes

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Chinese Physics Letters 2021年第1期38卷 121-124页

作者： Wei Zhang Chao Wang Jian-Wei Lian Jun Jiang An-Quan Jiang State Key Laboratory of ASIC&System School of MicroelectronicsFudan UniversityShanghai 200433China

The unipolar diode-like domain wall currents in LiNbO3 single-crystal nanodevices are not only attractive in terms of their applications in nonvolatile ferroelectric domain wall memory,but also useful in half-wave and full-wave rectifier systems,as well as detector,power protection,and steady voltage *** traditional diodes,where the rectification functionality arises from the contact between n-type and p-type conductors,which are unchanged after off-line production,ferroelectric domain wall diodes can be reversibly created,erased,positioned,and shaped,using electric *** demonstrate such functionality using ferroelectric mesa-like cells,formed at the surface of an insulating X-cut LiNbO_(3) single *** the application of an in-plane electric field above a coercive field along the polar Z axis,the domain within the cell is reversed to be antiparallel to the unswitched bottom domain via the formation of a conducting domain *** wall current was rectified using two interfacial volatile domains in contact with two side Pt *** the nonvolatile inner domain wall,the interfacial domain walls disappear to turn off the wall current path after the removal of the applied electric field,or under a negative applied voltage,due to the built-in interfacial imprint *** novel devices have the potential to facilitate the random definition of diode-like elements in modern large-scale integrated circuits.

关键词： switched ferroelectric interfacial

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A Ferroelectric Domain-Wall Transistor

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Chinese Physics Letters 2023年第3期40卷 82-86页

作者：欧阳俊孙杰李一鸣江安全 State Key Laboratory of ASIC&System School of MicroelectronicsFudan UniversityShanghai 200433China

On the basis of novel properties of ferroelectric conducting domain walls,the domain wall nanoelectronics emerges and provides a brand-new dimension for the development of high-density,high-speed and energy-efficient *** in-memory computing,three-terminal devices with both logic and memory functions such as transistors purely based on ferroelectric domain walls are urgently ***,a prototype ferroelectric domain-wall transistor with a well-designed coplanar electrode geometry is demonstrated on epitaxial Bi Fe O_(3)thin *** the logic function,the current switching between on/off states of the transistor depends on the creation or elimination of conducting domain walls between drain and source *** the data storage,the transistor can maintain nonvolatile on/off states after the write/erase operations,providing an innovative approach for the development of the domain wall nanoelectronics.

关键词： drain walls ferroelectric

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Ferroelectric domain wall memory

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Chinese Physics B 2023年第12期32卷 14-20页

作者：李一鸣孙杰江安全 State Key Laboratory of ASIC&System School of MicroelectronicsFudan UniversityShanghai 200433China

Ferroelectric domain walls appear as sub-nanometer-thick topological interfaces separating two adjacent domains in different orientations,and can be repetitively created,erased,and moved during programming into different logic states for the nonvolatile memory under an applied electric field,providing a new paradigm for highly miniaturized low-energy electronic *** some specific conditions,the charged domain walls are conducting,differing from their insulating bulk *** the past decade,the emergence of atomic-layer scaling solid-state electronic devices is such demonstration,resulting in the rapid rise of domain wall *** review aims to the latest development of ferroelectric domain-wall memories with the presence of the challenges and opportunities and the roadmap to their future commercialization.

关键词： domain wall memory ferroelectric

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A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration

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Journal of Semiconductors 2012年第10期33卷 116-121页

作者：张逸文陈迟晓余北叶凡任俊彦 State Key Laboratory of ASIC&System Microelectronics Science and Technology Innovation Platform Fudan University

Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this *** algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input *** detected sample-time error is corrected by a voltage-controlled sampling *** experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after *** calibration convergence time is about 20000 sampling intervals.

关键词： sample-time error analog-to-digital converter correlation calibration time-interleaved

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A fourth-order bandwidth-reconfigurable delta-sigma modulator for audio applications

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Journal of Semiconductors 2012年第7期33卷 74-79页

作者：王俊乾杨海峰魏蕊许俊任俊彦 State Key Laboratory of ASIC&System Fudan University Microelectronics Science and Technology Innovation Platform Fudan University

A single loop fourth-order delta-sigma modulator is presented for audio applications. A reconfigurable mechanism is adopted for two bandwidth-based modes （8 kHz/16 kHz）. Manufactured in the SM1C 0.13μm CMOS mixed signal process, the chip consumes low power （153.6 μW） and occupies a core area of 0.98×0.46 mm2. The presented modulator achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode, as well as a 90.2 dB SNR and 86 dB dynamic range in 8 kHz mode. The designed modulator shows a very competitive figure of merit among state-of-the-art low voltage modulators.

关键词： delta-sigma modulator feedforward architecture reconfiguration switched capacitor bootstrappedswitch

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FPGA-based Convolution Neural Network for Traffic Sign Recognition 12

FPGA-based Convolution Neural Network for Traffic Sign Recog...

引用

2017 IEEE 12th International Conference on asic

作者： Yuchen Yao Zhiqian Zhang Zhen Yang Jian Wang Jinmei Lai State Key Laboratory of ASIC&System Fudan University

ISBN: (纸本)9781509066261;9781509066254

Due to the rise in the number of vehicles in the past few years,the frequency of traffic accident has increased as well,resulting in huge *** a means to improve traffic safety,advanced driver assistance system(ADAS)has gradually gained more ***,it is difficult for traditional traffic sign recognition algorithms to achieve high accuracy in the ADAS whose scenarios are various in the practical *** most current methods based on convolution neural network(CNN) for traffic sign recognition has large amount of parameters,making its implementation on resource-limited hardware platform *** this work,we present a FPGA-based convolution neural network module for the recognition of traffic signs in *** results shows that the accuracy rate of the model is 98.1%,the total number of parameters is 4.7 M,only accounting for 12.5% of Alex Net,and the number of calculation in single forward transmission is 703.2 M,which takes up 61.4% of Alex Net.

关键词： CNN FPGA-based Convolution Neural Network for Traffic Sign Recognition

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The Power of Graph Signal Processing for Chip Placement Acceleration

arXiv

引用

arXiv 2025年

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. Copyright © 2025, The Authors. All rights reserved.

关键词： Nonlinear programming

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Epitaxial Growth of High-Quality Silicon Films on Double-Layer Porous Silicon

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Chinese Physics Letters 2001年第11期18卷 1507-1509页

作者： HUANG Yi-Ping ZHU Shi-Yang LI Ai-Zhen WANG Jin HUANG Jing-Yun YE Zhi-Zhen Department of Microelectronics ASIC&System State Key LaboratoryFudan UniversityShanghai 200433 State Key Laboratory of Silicon Material Science Zhejiang UniversityHangzhou 310027

The epitaxial growth of a high-quality silicon layer on double-layer porous silicon by ultra-high vacuum/chemical vapour deposition has been reported. The two-step anodization process results in a double-layer porous silicon structure with a different porosity. This double-layer porous silicon structure and an extended low-temperature annealing in a vacuum system was found to be helpful in subsequent silicon epitaxial growth. X-ray diffraction,cross-sectional transmission electron microscopy and spreading resistance testing were used in this work to study the properties of epitaxial silicon layers grown on the double-layer porous silicon. The results show that the epitaxial silicon layer is of good crystallinity and the same orientation with the silicon substrate and the porous silicon layer.

关键词： porous double vacuum

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