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检索条件"机构=State Key Lab of ASIC&System"
846 条 记 录,以下是21-30 订阅
排序:
A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DVS Applications
A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DV...
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IEEE International Symposium on Circuits and systems (ISCAS)
作者: Xi Cheng Shu Cao Shangmei Wang Xiaoyang Zeng Wenhong Li Mingyu Wang State Key Lab of ASIC & System Fudan University Shanghai China
This paper proposed a hardware-algorithm co-design of an event-driven Spiking Neural Network (SNN) accelerator with structured sparsity for Dynamic Vision Sensors (DVS) applications. The accelerator can accommodate up... 详细信息
来源: 评论
TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization
TransFRU: Efficient Deployment of Transformers on FPGA with ...
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Asia and South Pacific Design Automation Conference
作者: Hongji Wang Yueyin Bai Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China
Transformer-based models have achieved huge success in various artificial intelligence (AI) tasks, e.g., natural language processing (NLP) and computer vision (CV). However, transformer-based models always suffer from...
来源: 评论
A Lossless Compression Algorithm with Hardware Implementation for Dynamic Vision Sensor
A Lossless Compression Algorithm with Hardware Implementatio...
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IEEE International Symposium on Circuits and systems (ISCAS)
作者: Zewei Ding Shangmei Wang Yujie Cai Xiaoyang Zeng Wenhong Li Mingyu Wang State Key Lab of ASIC & System Fudan University Shanghai China
Nowadays, with the increase resolution of Dynamic Vision Sensor (DVS), efficient compression algorithm for event stream is needed urgently. Conventional DVS system encodes event data in address event representation (A... 详细信息
来源: 评论
SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design
SDAcc: A Stable Diffusion Accelerator on FPGA via Software-H...
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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
作者: Hao Zhou Yang Liu Hongji Wang Enhao Tang Shun Li Yifan Zhang Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China
Stable Diffusion has become one of the mainstream image synthesis algorithms. The mainstream computing platform for Stable Diffusion is GPU. However, the deployment of Stable Diffusion on GPU still faces the problems ... 详细信息
来源: 评论
Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier
Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference wi...
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Asia and South Pacific Design Automation Conference
作者: Zihang Ma Zeyu Li Yuanfang Wang Yu Li Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China
Instant-NGP is the state-of-the-art (SOTA) algorithm of Neural Radiance Field (NeRF) and shows great potential to be adopted in ARNR. However, the high cost of memory and computation limits Instant-NGP’s implementati...
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A Broadband and High Speed CML Divider with Inductor Peaking in 40-nm SMIC  16
A Broadband and High Speed CML Divider with Inductor Peaking...
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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022
作者: Shen, Chao Jiang, Yang Wu, Tianxiang Cui, Huarui Ma, Shunli Ren, Junyan Fudan University State-Key Laboratory of ASIC&System Shanghai201203 China The 24th Research Institute of China Electronics Technology Group Corporation Chongqing400060 China
High-frequency broadband current-mode logic static divider circuit fabricated in CMOS 40-nm is presented. In the proposed circuit, inductance peaking technology is utilized to improve the locking frequency and working... 详细信息
来源: 评论
A Pin Photodetector Based on a RF-SOI Substrate
A Pin Photodetector Based on a RF-SOI Substrate
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2022 China Semiconductor Technology International Conference, CSTIC 2022
作者: Chou, J.J. Wan, J. School of Information Science and Engineering Fudan University State Key Lab of Asic and System Shanghai China
In this work, A lateral PIN diode is fabricated based on the RF-SOI substrate. The diode is further used in UV photodetection and high-speed optical communication. It exhibits excellent linearity under various light i... 详细信息
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Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2025年
作者: Gu, Hao Gu, Jian Peng, keyu Chen, Jianli Yang, Jun Zhu, Ziran Southeast University National ASIC System Engineering Research Center School of Integrated Circuits Nanjing210096 China Fudan University State Key Lab of ASIC and System Shanghai200433 China
Field-programmable gate array (FPGA) macro placement holds a crucial role within the FPGA physical design flow since it substantially influences the subsequent stages of cell placement and routing. With the increasing... 详细信息
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A 6b 800MS/s SAR ADC With Speed-Enhanced SAR Logic and Grouped DAC Capacitors  16
A 6b 800MS/s SAR ADC With Speed-Enhanced SAR Logic and Group...
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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022
作者: Zhang, Yuxuan Zhao, Yutong Lan, Jingchao Ye, Fan Xie, Yufeng Ren, Junyan State Key Lab. of ASIC & System Fudan University Shanghai China School of Microelectronics Fudan University
This paper presents a 6-bit 800MS/s successive approximation register (SAR) analog-to digital converter (ADC) in 28nm CMOS with grouped digital-to-analog converter (DAC) capacitor array. High-speed operation is achiev... 详细信息
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High Efficient Automatic Power/Ground Layout Routing Algorithm for Analog ICS
High Efficient Automatic Power/Ground Layout Routing Algorit...
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2023 China Semiconductor Technology International Conference, CSTIC 2023
作者: Zuo, Jiaxin. Li, Fei. Wan, Jing. Fudan University State Key Lab of Asic and System School of Information Science and Engineering Shanghai China Suzhou Foohu Technology Co. Ltd. China
In this work, we explored an efficient automatic layout routing algorithm for connecting the power and ground pins in analog integrated circuits. A rectilinear minimal spanning tree (RMST) algorithm for two sets of pi... 详细信息
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