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检索条件"机构=State Key Lab of ASIC&System"
846 条 记 录,以下是31-40 订阅
排序:
High-Dimensional Analog Circuit Sizing via Bayesian Optimization in the Variational Autoencoder Enhanced Latent Space
High-Dimensional Analog Circuit Sizing via Bayesian Optimiza...
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Electronics Design Automation (ISEDA), International Symposium of
作者: Wangzhen Li Zhaori Bi Xuan Zeng Microelectronics Department State Key Lab of ASIC & System Fudan University Shanghai China
High-dimensional analog circuit sizing with machine learning-based surrogate models suffers from the high sampling cost of evaluating expensive black-box objective functions in huge design spaces. This work addresses ... 详细信息
来源: 评论
SDformer: Efficient End-to-End Transformer for Depth Completion
arXiv
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arXiv 2024年
作者: Qian, Jian Sun, Miao Lee, Ashley Li, Jie Zhuo, Shenglong Chiang, Patrick Yin State Key Lab of ASIC & System Fudan University Shanghai China PhotonIC Technologies
Depth completion aims to predict dense depth maps with sparse depth measurements from a depth sensor. Currently, Convolutional Neural Network (CNN) based models are the most popular methods applied to depth completion... 详细信息
来源: 评论
PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design
PRAD: A Bayesian Optimization-based DSE Framework for Parame...
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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
作者: Bingbing Peng Shaoyang Sun Yuan Dai Jingyuan Li Yunhui Qiu Kaihang Wang Wenbo Yin Lingli Wang State Key Lab of ASIC and System Fudan University China
Coarse-Grained Reconfigurable Architecture (CGRA) is a domain-specific reconfigurable architecture. Generally, the CGRA architecture consists of IO, memory, coarse-grained processing element (PE), and interconnect. Us...
来源: 评论
HierSyn: Fast Synthesis for Large Hierarchical Designs  15
HierSyn: Fast Synthesis for Large Hierarchical Designs
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15th IEEE International Conference on asic, asicON 2023
作者: Zhang, Yishan Zhang, Zhiyong Wu, Chang Fudan University State-Key Lab of ASIC and System School of Microelectronics Shanghai200433 China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai200433 China
As design goes into multi-billion transistors, the synthesis runtime becomes an important issue, particularly for design verification and prototyping, as one may run the synthesis many times with design change. Module... 详细信息
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Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGA
Moth: A Hardware Accelerator for Neural Radiance Field Infer...
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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
作者: Yuanfang Wang Yu Li Haoyang Zhang Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China
Neural Radiance Field (NeRF) is a state-of-the-art algorithm in the field of novel view synthesis and has the potential to be used in AR/VR. However, the inference of NeRF is time-consuming. Motivated by resource-cons...
来源: 评论
A Decision-Based CORDIC Hardware for Arc Tangent Calculation
A Decision-Based CORDIC Hardware for Arc Tangent Calculation
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International Conference on asic
作者: Haoyu Wu Liyu Lin Haodong Sun Xiaoyang Zeng Yun Chen State Key Lab of ASIC & System Fudan University Shanghai China
The COordinate Rotation DIgital Computer (CORDIC) simplifies the elementary function using bit-shift operation and addition. However, the iteration increases with the accuracy and causes a long latency. In this paper,...
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FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks
FET-OPU: A Flexible and Efficient FPGA-Based Overlay Process...
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IEEE International Conference on Computer-Aided Design
作者: Yueyin Bai Hao Zhou Keqing Zhao Hongji Wang Jianli Chen Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China
There are already some works on accelerating transformer networks with field-programmable gate array (FPGA). However, many accelerators focus only on attention computation or suffer from fixed data streams without fle...
来源: 评论
g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning
g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-...
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IEEE International Conference on Communications (ICC)
作者: Yueyin Bai Hao Zhou Ruiqi Chen Kuangjie Zou Jialin Cao Haoyang Zhang Jianli Chen Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China
Transformer-based models suffer from large num-ber of parameters and high inference latency, whose deployment are not green due to the potential environmental damage caused by high inference energy consumption. In add...
来源: 评论
UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization
UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Opt...
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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
作者: Yuan Dai Yunhui Qiu Qilong Zhu Jingyuan Li Wenbo Yin Lingli Wang State Key Lab of ASIC and System Fudan University Shanghai China
Temporal Coarse-Grained Reconfigurable Architecture (CGRA) is a typical category of CGRA that supports single-cycle context switching and time-multiplexing hardware resources to perform both spatial and temporal compu...
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LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks
LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for T...
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International Conference on Field Programmable Logic and Applications
作者: Yueyin Bai Hao Zhou Keqing Zhao Manting Zhang Jianli Chen Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China
Existing accelerators for transformer networks with field-programmable gate array (FPGA) either focus only on attention computation or suffer from fixed data streams without flexibility. Moreover, compression and appr...
来源: 评论