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A VLIW Architecture Stream Cryptographic Processor for Information Security

China Communications 2019年第6期16卷 185-199页

作者： Longmei Nan Xuan Yang Xiaoyang Zeng Wei Li Yiran Du Zibin Dai Lin Chen ASIC&System State Key Laboratory of Fudan University Shanghai 201203China Institute of Information Science and Technology Zhengzhou 450001China Jiangnan Institute of Computing Technology WuXi 214083China

As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is *** implementation methods,such as FPGA,GPP and asic,provide a good support,but they could not achieve a better tradeoff between high speed processing and high *** has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very *** paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher *** analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher *** proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic *** the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher *** has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 *** kinds of stream ciphers were realized in the *** key stream generation throughput of Grain-80,W7,MICkey,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,*** test result shows that the processor presented can achieve good tradeoff between high performance and flexibili

关键词： stream cipher VLIW architecture processor reconfigurable application-specific instruction-set

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Design of Three High-Performance Concurrent Systolic Arrays for Band Matrix Multiplication

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电子学报(英文版) 2005年第4期14卷 559-563页

作者： YANG Yun ZHAO Wenqing ASIC ＆ System State-Key-Lab Micro-Electronics Department Fudan University Shanghai 200433 China

Band matrix multiplication is widely used in the concurrent system. But traditional Kung-Leiserson systolic array for band matrix multiplication cannot realize high cell efficiency because only about 1/3 cells are operated in each step. Thus three alternative designs are presented based on the ideas of "Matrix compression" and "Super pipelined". These new arrays arrange and compress the data matrix skillfully, and add the Processing elements (PE) or readjust the operation sequence to increase the cell efficiency. These changes realize higher cell efficiency and faster operation speed with more intricate architectures. The results show that the best systolic array for band matrix multiplication can use almost 100% processing elements in each step, which is nearly triplication of the traditional Kung-Leiserson system. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

关键词：带状矩阵乘法矩阵压缩操作次序 Kung-Leiserson系统 DSP 数字信号处理器

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A Photoelectric-Stimulated MoS_(2) Transistor for Neuromorphic Engineering

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Research 2019年第1期2019卷 273-282页

作者： Shuiyuan Wang Xiang Hou Lan Liu Jingyu Li Yuwei Shan Shiwei Wu David Wei Zhang Peng Zhou ASIC&System State Key Lab. School of MicroelectronicsFudan UniversityShanghai 200433China Department of Physics State Key Laboratory of Surface PhysicsKey Laboratory of Micro and Nano Photonic Structures(Ministry of Education)and Institute for Nanoelectronic Devices and Quantum ComputingFudan UniversityShanghai 200433China

The von Neumann bottleneck has spawned the rapid expansion of neuromorphic engineering and brain-like *** serve as bridges for information transmission and connection in the biological nervous *** direct implementation of neural networks may depend on novel materials and devices that mimic natural neuronal and synaptic *** exploiting the interfacial effects between MoS_(2) and AlOx,we demonstrate that an h-BN-encapsulated MoS_(2) artificial synapse transistor can mimic the basic synaptic behaviors,including EPSC,PPF,LTP,and *** optoelectronic spikes enable simulation of synaptic gain,frequency,and weight *** Pavlov classical conditioning experiment was successfully simulated by electrical tuning,showing associated learning *** addition,h-BN encapsulation effectively improves the environmental time stability of our *** h-BN-encapsulated MoS_(2) artificial synapse provides a new paradigm for hardware implementation of neuromorphic engineering.

关键词： tuning optoelectronic artificial

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Effect of chlorine residue on electrical performance of atomic layer deposited hafnium silicate

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JOURNAL OF APPLIED PHYSICS 2008年第11期103卷 114102-114102-4页

作者： Sun, Qing-Qing Zhang, Chi Dong, Lin Shi, Yu Ding, Shi-Jin Zhang, David Wei Fudan Univ Dept Microelect State Key Lab ASIC & System Shanghai 200433 Peoples R China

Hafnium tetrachloride is one of the most commonly used precursors for atomic layer deposition of hafnium based gate dielectrics. According to the previously reported experimental result, chlorine residue is almost unavoidably incorporated and piled up near the interface. We performed first-principles calculations to study the effect of chlorine residue in HfSiO(4), which explained the experimental observations. The chlorine at interstitial site serves as a source of negative fixed charge, while the chlorine at oxygen substitutional site changes its charge state depending on the position of electron chemical potential within the HfSiO(4) band gap, which possibly enlarges the hysteresis of the gate dielectrics. Moreover, chlorine incorporation also reduces the band gap of HfSiO(4) by inducing lattice strain. (C) 2008 American Institute of Physics.

关键词： CHLORINE HAFNIUM SILICATES DIELECTRICS ELECTRIC charge & distribution HYSTERESIS

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A Robust and Low Complexity Implementation of Synchronization for DVB-T Receiver

A Robust and Low Complexity Implementation of Synchronizatio...

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2005 6th International Conference on asic

作者： Huarong Zheng Jiefeng Yan Jianing Su Xiaoyang Zeng ASIC & System State Key Lab Fudan University

ISBN: (纸本)0780392108

A robust low-complexity synchronization architecture for Digital Terrestrial Video Broadcasting (DVB-T) systems over fading channel is presented in this *** consists of symbol timing recovery, sampling clock recovery and carrier frequency *** this paper,all these problems are analyzed and an optimum system solution is *** results show that the proposed scheme works well even in the presence of 10% carrier frequency offset(CFO) and 330 ppm sampling frequency offset(SFO).Meanwhile,the circuit area is reduced by more than 40%compared to the conventional scheme.

关键词： DVB-T synchronization

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Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation

Simplified AES Algorithm Resistant to Zero-Value Power Analy...

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Jia Zhao Xiaoyang Zeng Jun Han Jun Chen State-Key Lab of ASIC and System Fudan University

ISBN: (纸本)1424401615

This paper proposes a simplified AES algorithm resistant to zero-value DPA(Differential Power Analysis) attack and its VLSI *** paper makes some improvements to the additive masking AES algorithm to decrease its ***,such methods as module reuse and calculation order alteration are used to reduce chip area while maintaining its *** the HHNEC 0.25μm CMOS process,the scale of the design is about 43K equivalent gates and its system frequency is up to *** throughputs of the 128-bit data encryption and decryption are as high as 470Mbit/s.

关键词： Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation AES

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New Methods of FPGA co-verification for system on Chip(SoC)

New Methods of FPGA co-verification for System on Chip(SoC)

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2005 6th International Conference on asic

作者： Lin Yi-fan Zeng Xiao-yang Wu Min Chen Jun Bao Rencheng State Key Lab of ASIC & System Fudan University

ISBN: (纸本)0780392108

With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI Design,and it requires much more portion of time within the life circle of chip *** time spent on the FPGA verification should be reduced to achieve a more efficient Time-to-Market for the IC product. Therefore,Several strategies using both dynamic and static methods to execute this verification are proposed in this *** using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping,the software verification is accelerated.A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system *** this paper,experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process.

关键词： SoC Co-Verification Interrupt Vectors Remapping Software Monitoring Bus Monitoring

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A Scalable Design of RSA Crypto-coprocessor

A Scalable Design of RSA Crypto-coprocessor

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Yehua Gu Xiaoyang Zeng Jun Han Yongxin Ma Jia Zhao State Key Lab of ASIC ＆ System Fudan University

ISBN: (纸本)1424401607

A scalable design of RSA Crypto-coprocessor is presented in this paper,which supports variable keys up to 4096- *** analyzing and improving the modified multiple-word Montgomery multiplication algorithm,its pipeline architecture is optimized and critical path is greatly ***, its performance is much higher compared with previous work. Therefore,the proposed design is very suitable to the low-cost and high-performance RSA cryptosystem and can be easily implemented in VLSI technology.

关键词： PPE Controller A Scalable Design of RSA Crypto-coprocessor

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A Direct Conversion WLAN Receiver

A Direct Conversion WLAN Receiver

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2005 6th International Conference on asic

作者： Jingguang Wang Jinju Wang Yumei Huang Weilun Shen Xiaofeng Yi Zhiliang Hong State Key Lab of ASIC and System Fudan University

ISBN: (纸本)0780392108

A direct conversion receiver for WLAN 802.11b is presented in 0.18μm CMOS *** contains a complete receiver chain with low noise amplifier,I/Q mixer,programmable gain amplifier and base band filter.A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q *** reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f *** noise figure of receiver is 5.2dB,the UP3 is -l4.5dBm at high gain *** the supply voltage of 1.8V,the over all power consummation is about 100mW. The chip area with pads is 2.6mm×2.5mm.

关键词： CMOS direct conversion receiver WLAN low noise amplifier mixer programmable gain amplifier base band filter dc-offset 1/f noise.

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Hardware Friendly Algorithm of HR Real Time Stereo Matching for Automatic Drive 13

Hardware Friendly Algorithm of HR Real Time Stereo Matching ...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Liming Wang Hanrui Wang Yize Jin Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Stereo matching is a most challenging topic in artificial intelligence. Local algorithms are better than global ones with lower complexity and higher speed for HD real-time stereo matching. This paper proposes an optimized local stereo algorithm adaptive window disparity estimation with cross check(AWDE-CC). A region growth algorithm to fill bad pixels is also proposed which can bring an improvement of the performance in low texture regions efficiently. The average error rate of the generated disparity maps is approximately 8%.

关键词： Local stereo match adaptive window cross check region growth

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