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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Haodong Lu Qichang Mei Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China

Transformer-based models have achieved remarkable performance across various tasks, while the computational complexity presents an obstacle for deploying on resource-constrained devices. To this end, this paper proposes an efficient approximation framework termed NPLA for approximating non-linear operations during Transformer inference on hardware accelerators. Specifically, NPLA enables the approximation of non-linear operations using non-uniform piecewise linear functions and directly converts coefficients into LUTs for hardware implementation. Experimental results demonstrate that NPLA can reduce the hardware cost by 13.43× in LUTs and 1.98× in DSP compared to the state-of-the-art method.

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RLCkt: An Analog Circuit Automatic Sizing Sage Based on Reinforcement Learning

RLCkt: An Analog Circuit Automatic Sizing Sage Based on Rein...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Zuo, Wangge Liu, Lingge Li, Fei Huang, Yifei Zhang, Liqian Wan, Jing Fudan University School of Information Science and Engineering State Key Lab of Asic and System Shanghai200433 China Suzhou Foohu Technology Co. Ltd. Shanghai200433 China

ISBN: (纸本)9798350311006

Automated solutions for sizing analog circuits have gained significant interest due to the labor-intensive nature of the task in a typical design cycle, especially with technology development and circuit scaling. This study introduces the RLCkt, an Analog Circuit Automatic Sizing Sage, which utilizes reinforcement learning (RL) and the SPICE simulator to automatically adjusts design parameters to meet performance metrics. After several hours of training, RLCkt runs 94 times faster than a traditional generic algorithm with comparable performance. Additionally, its generalization capability surpasses that of state-of-the-art methods. © 2023 IEEE.

关键词： Reinforcement learning

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Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning

Automated Design of Complex Analog Circuits with Multiagent ...

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Design Automation Conference

作者： Jinxin Zhang Jiarui Bao Zhangcheng Huang Xuan Zeng Ye Lu State Key Lab. of ASIC & System School of Information Science and Technology Frontier Institute of Chip and System State Key Lab. of ASIC & System Microelectronics Department Fudan University Shanghai China

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It’s shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

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A Blockchain-Based Certificate system with Credit Self-Adjustment

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Wuhan University Journal of Natural Sciences 2023年第2期28卷 163-168页

作者： ZHOU Wang TAO Jun LI Xin School of Electronic Information Wuhan UniversityWuhan 430072HubeiChina State Key Lab of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China Data Science Research Center Duke Kunshan UniversityKunshan 215316JiangsuChina

Currently,digital certificate systems based on blockchain have been extensively developed and ***,most of them do not take into account the certificate *** evaluate the credibility of certificates issued by educational institutions,we propose a novel blockchain-based system with credit self-adjustment(BC-CS).In BC-CS,employers can provide feedback according to the performances of their employees(i.e.,students)holding different *** on the feedback,BC-CS automatically adjusts the certificate credits by using our proposed credit self-adjustment *** verify the feasibility of our proposed system,a decentralized application prototype has been developed on an Ethereum *** results demonstrate that the proposed system can fully support multistep accreditation and automatic adjustment for certificate credit.

关键词： blockchain certificate credit self-adjustment

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A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology

A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm ...

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International Conference on asic

作者： Bingrong Lyu Fan Ye Junyan Ren State Key Lab. of ASIC & System Fudan University Shanghai China

A 6-Gb/s half rate current mode logic (CML) transmitter has been designed in TSMC 28nm CMOS technology, which employs a 3-tap 3-bit feed forward equalizer (FFE), an analog duty cycle correction module (DCC) for half rate clock and a 5-bit output impedance calibration module for 100-ohm differential load. Post-layout simulation indicates that the FFE could compensate for up to 4.7dB channel loss at 3GHz while maintaining 410mVpp eye height. The DCC module could corrects±30% duty cycle mismatch and max deviation of the calibrated impedance is 2.7%. Implemented in 28nm CMOS technology, the transmitter delivers 6-Gb/s data (2 15 -1 PRBS) with 4.7dB channel attenuation at 3GHz. The transmitter (excluding clock generating PLL) consumes 27.67mA from 0.9V supply and occupies a die area of 214μm * 108μm.

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Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling 14

Efficient High-Level Synthesis of Approximate Computing Circ...

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14th IEEE International Conference on asic, asicON 2021

作者： Li, Yingqi Yang, Fan Yan, Changhao Zeng, Xuan Fudan University State Key Lab of Asic System 201203 China

ISBN: (纸本)9781665411493

High-Level Synthesis (HLS) of approximate computing circuits generates circuits based on functional units such as adders and multipliers. An approximate library containing approximate functional units is firstly built, and then an algorithm is employed to search in the library, solving the binding problem of HLS and finally generating an approximate circuit that meets design specifications. In this paper, we propose a discrete-input and multi-fidelity Bayesian optimization (BO) approach to solve this design space exploration problem. Since the input of the algorithm is discrete functional units in the approximate library, we modify the kernel function of Gaussian Process (GP) model in BO. In addition, we adopt a multi-fidelity strategy to speed up the optimization process, which is proved to be effective and efficient according to our experimental results. © 2021 IEEE.

关键词： High level synthesis

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GSW: A high performance IQA index based on global and saliency window similarity 3

GSW: A high performance IQA index based on global and salien...

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2021 3rd International Conference on Artificial Intelligence and Computer Science, AICS 2021

作者： Fan, Yibo Meng, Zihao The State Key Lab of ASIC and System Fudan University Shanghai China

Perceptual image quality assessment (IQA) attracts significant attention in recent years. It is proved that both global score and an image’s visual saliency (VS) are consistent with subjective evaluation. The global quality score reflects the consistency of the overall structure between two images, and VS map contributes complementarily in evaluating perceptual quality. This paper presents an effective IQA index based on global and saliency window similarity, namely GSW. It chooses VS map as an image feature and uses a special strategy to draw the saliency window with largest significancy. Meanwhile, the background area is taken into account to guarantee the robustness of the quality score. Experimental results on four most widely used databases verify that, compared with state-of-the-art IQA methods, GSW performs consistently well can provide more accurate quality prediction with a low computational complexity. © Journal of Physics: Conference Series 2021.

关键词： Image quality

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An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC

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Frontiers of Information Technology & Electronic Engineering 2022年第1期23卷 134-144页

作者： Mengni BIE Wei LI Tao CHEN Longmei NAN Danyang YANG Information Engineering University Zhengzhou450001China State Key Lab of ASIC and System Fudan UniversityShanghai200000China

RSA and ellipse curve cryptography(ECC)algorithms are widely used in authentication,data security,and access *** this paper,we analyze the basic operation of the ECC and RSA algorithms and optimize their modular multiplication and modular inversion *** then propose a reconfigurable modular operation architecture,with a mix-memory unit and double multiply-accumulate structures,to realize our unified,asymmetric cryptosystem structure in an operational *** with 55-nm CMOS process,our design runs at 588 MHz and requires only 437801µm2 of hardware *** proposed design takes 21.92 and 23.36 mW for 2048-bit RSA modular multiplication and modular inversion respectively,as well as 16.16 and 15.88 mW to complete 512-bit ECC dual-field modular multiplication and modular inversion *** is more energy-efficient and flexible than existing single algorithm *** with existing multiple algorithm units,our proposed method shows better *** operation unit is embedded in a 64-bit RISC-V processor,realizing key generation,encryption and decryption,and digital signature functions of both RSA and *** proposed design takes 0.224 and 0.153 ms for 256-bit ECC point multiplication in G(p)and G(2^(m))respectively,as well as 0.96 ms to complete 1024-bit RSA exponentiation,meeting the demand for high energy efficiency.

关键词： Modular operation unit Reconfigurable High energy efficiency

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A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits 14

A Fast Aging-aware Static Timing Analysis Prediction Frame o...

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14th IEEE International Conference on asic, asicON 2021

作者： Hu, Jiahui Yan, Changhao Guo, Chao Jiang, Ronggui Zhou, Dian Zeng, Xuan Fudan University State Key Lab of ASIC and System Shanghai201203 China

ISBN: (纸本)9781665411493

In the digital circuit design stage, the analysis and prediction of aging effects can help improve circuit reliability. In this paper, we firstly propose a fast aging-aware static timing analysis prediction approach for digital integrated circuits. Although the aging-aware analysis prediction model can be readily formulated into an optimization problem of the least square solution, the main challenge is the problem scale. A critical path selecting and sampling scheme is adopted to reduce dimensionality. Then we develop a solver based on Randomized Kaczmarz algorithm to realize an efficient solution. Based on industrial designs, experimental results for aging-aware static timing analysis show 9.95× speedup over the state-of-the-art method with similar accuracy. © 2021 IEEE.

关键词： Forecasting

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Research of Scale Recurrent Generative Network on Image Inpainting 14

Research of Scale Recurrent Generative Network on Image Inpa...

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14th IEEE International Conference on asic, asicON 2021

作者： Zhang, Ziyi Lyu, Dong Xu, Wei Fudan University State Key Lab of ASIC and System Shanghai200433 China

ISBN: (纸本)9781665411493

Existing learning-based inpainting methods have recently reached notable success in filling irregular holes. However, the quantity of network parameters in these methods also grows rapidly, thus making them difficult for training and deployment on resource-limited platforms. In this paper, we propose a Scale Recurrent Generative Network (SRGN), in which a new scale recurrent structure is raised and deployed on top of the general learning-based inpainting methods. The scale recurrent procedure stores the context information in different scales to achieve better memorability while keeping the network parameters in the same order of magnitude. To add the iterations on scale dimension, we combine max pooling and average pooling in the downsampling procedure and introduce scale factor in the loss function. The qualitative and quantitative comparisons on the Places2 dataset show that the texture and detail of our generated image are significantly improved in comparison with peer works. © 2021 IEEE.

关键词： Textures

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