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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Chen, Weijie Huang, Haishan Wei, Min Zou, Peng Chen, Jianli Fuzhou University College of Computer and Data Science Fuzhou350108 China Fudan University State Key Lab of Asic & System Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Timing optimization plays an essential role in very large scale integration (VLSI) design closure. Traditional placement algorithms seldom consider the complex timing constraints and thus may lead to inferior timing results. In this paper, we propose a timing-aware virtual path optimization strategy for VLSI global placement. The proposed algorithm uses a novel virtual net method and simultaneously optimizes the timing and wirelength. We evaluate our results on the ICCAD 2015 contest benchmarks and industrial benchmarks. Compared with the widely used net-weighting method, experimental results show that our algorithm achieves not only a 11.2% improvement in worst negative slack but also a 15.9% in total negative slack. © 2022 IEEE.

关键词： VLSI circuits

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A Gaussian Rocess and Multi-Swarm Optimizer Assisted Optimization Approach for Analog Circuit Design

A Gaussian Rocess and Multi-Swarm Optimizer Assisted Optimiz...

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2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Fu, Xu Yan, Changhao Zhou, Dian Zeng, Xuan Fudan University State Key Lab of Asic & System Shanghai201203 China University of Texas Department of Electrical Engineering DallasTX United States

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

In this paper, we propose an analog circuit synthesis approach that consists of a Gaussian process and niching migratory multi-swarm optimizer assisted differential evolution algorithm. Instead of building an artificial neural network (ANN) to perform a local minimum search by sampling a large number of samples in the local area, we use samples simulated before to build a Gaussian process model and combine the Gaussian process model and niching migratory multi-swarm optimizer to exploit the local area. The weighted expected improvement function is selected as the criterion to judge which point is more worthy of simulation. Compared to the ANN assisted optimization system, our proposed method reduces the simulation time by up to 15×. © 2022 IEEE.

关键词： Neural networks

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An Agile Instruction Set Extension Method Based on the RISC-V Processor 4

An Agile Instruction Set Extension Method Based on the RISC-...

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4th IEEE International Conference on Electronics Technology, ICET 2021

作者： Hu, Bowen Chen, Yun Zeng, Xiaoyang Fudan University State Key Lab of Asic System School of Microelectronics Shanghai China

ISBN: (纸本)9781728176734

The slowdown in Moore's Law scaling has triggered a growing awareness of domain-specific processors. One of the very promising techniques is the instruction set extension. RISC-V, as an open and simple instruction set architecture, is ideally suited as a basis for building domain-specific instruction-set processors. In this paper, we construct a framework based on the RISC-V processor that can receive data flow graph-based descriptions and automatically perform instruction set extensions. The framework is based on open-source software dependencies and is able to better interact with application codes, thus bridging the barrier between the application and the underlying microarchitecture of the processor. To evaluate the framework, a quantitative analysis of the Fast Fourier Transform algorithm is performed and the instruction set extension is applied with the framework proposed in this paper. By applying the methods in this paper to accelerate this commonly used digital signal processing algorithm, the runtime was reduced by 62%. © 2021 IEEE.

关键词： Graphic methods

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An Efficient Global Router for Large-scale Congestion-driven Routing 16

An Efficient Global Router for Large-scale Congestion-driven...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Huang, Haishan Chen, Weijie Cai, Zhijie Huang, Jiarong Chen, Jianli Fuzhou University College of Computer and Data Science Fuzhou350108 China Fudan University State Key Lab of Asic & System Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In the very large scale integration (VLSI) global routing stage, one of the most critical considerations is how to obtain a proper balance between routing quality and runtime. In this paper, we adopt a multi-threading technique to accelerate various subphases of global routing. To ensure the robustness of routing results, we add a stage called congestion and wire length aware breaking circles algorithm while ensuring to remove the most congested or longest wire segment in the loops. Since routing congestion is the most critical constraint in the global routing phase, we present two accurate cost models to evaluate the routing resources, which can effectively reduce the congestion of routing results. The experiment shows that our proposed method reduces the violations by 28.3% and achieves a 2x faster runtime in benchmarks of the ISPD'19 contest compared with CUGR. © 2022 IEEE.

关键词： VLSI circuits

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Analysis and Design of Continuous-Time Incremental Sigma-Delta Modulators with Extended Counting Technique 16

Analysis and Design of Continuous-Time Incremental Sigma-Del...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Wei, Tingting Wang, Qiong Yuan, Zhu Lai, Jiahui Zeng, Xiaoyang Hong, Zhiliang Fudan University Room State Key Lab. of Asic and System Dept. of Microelectronics NO. 825 Zhangheng Rd Pudong District Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Continuous-time incremental sigma-delta modulators are analyzed in this paper, and it is found that the resolution of the modulator can be effectively improved by extended counting of its residual error, similar to its discrete counterparts. Further analysis shows except for the discrete-to-continuous equivalence of the modulator, a similar but reversed equivalence is required for the digital reconstruction filter to correctly quantify the signal. Based on these analyses, this paper designs a second-order incremental continuous-time sigma-delta modulator and its digital reconstruction filter. Simulation results show that this modulator achieves a peak signal-to-noise ratio (SNR) of 102dB at a conversion rate of 7.8KSample/s. The SNR is improved by 35dB compared with continuous-time incremental sigma-delta modulators without extended counting. Using a 1.8V power supply, the power consumption of the modulator is 108μW only. © 2022 IEEE.

关键词： Modulators

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Research on Supply Chain Traceability system Based on Semantic Multi-Blockchain and Pre-OnChain Data Verification

Research on Supply Chain Traceability System Based on Semant...

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IEEE/ACM Int'l Conference on & Int'l Conference on Cyber, Physical and Social Computing (CPSCom) Green Computing and Communications (GreenCom)

作者： Lulu Li Huan Qu Wei Wang Junyu Wang Zhihui Wang Bin Nong School of Computer Science Fudan University Shanghai China State Key Laboratory of ASIC&System Fudan University Shanghai China Department of IoT Zhuhai Fudan Innovation Institute Zhuhai China

Blockchain-based supply chain traceability systems are characterized by decentralization, transparency, and immutability. However, if all nodes replicate the entire ledger, it would result in significant storage overhead. Some nodes might be forced to exit the system due to inadequate storage resources. Additionally, the chained structure of blockchain implies that query delays will significantly increase as the volume of data grows. Furthermore, the immutable nature of blockchain demands a higher level of accuracy in the original data within the traceability system, as once erroneous data is uploaded to the blockchain, it cannot be altered or removed. In this paper, First, we analyze the requirements of supply chain business scenarios and the characteristics of traceability data. Then, we propose a semantic multi-chain storage architecture, categorizing data from different business entities into respective semantic side-chains, thereby addressing issues such as insufficient node storage and on-chain data explosion. Second, We introduce a semantic aggregation storage optimization technique, consolidating data with identical semantic keys into a single block, thereby reducing the number of blocks accessed during queries and improving query efficiency. Lastly, for the first time, we introduce a pre-onchain data reliability verification mechanism based on data characteristics. The results indicate that the proposed solution can offer reduced on-chain storage space, faster query speeds, and enhanced reliability of the original data sources.

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The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

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Highly sensitive and stable β-Ga_(2)O_(3) DUV phototransistor with local back-gate structure and its neuromorphic application

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Nano Research 2022年第10期15卷 9359-9367页

作者： Xiao-Xi Li Guang Zeng Yu-Chun Li Qiu-Jun Yu Meng-Yang Liu Li-Yuan Zhu Wenjun Liu Ying-Guo Yang David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433China Shanghai Synchrotron Radiation Facility(SSRF) Zhangjiang LabShanghai Advanced Research Institute&Shanghai Institute of Applied PhysicsChinese Academy of SciencesShanghai 201204China

Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence *** order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally *** phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm ***,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance ***,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial ***β-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.

关键词： β-Ga_(2)O_(3)phototransistors local back-gate responsivity stability photonic synapse

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Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints 23

Toward Optimal Filler Cell Insertion with Complex Implant La...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Peng Zou Guohao Chen Zhifeng Lin Jun Yu Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China

ISBN: (纸本)9798350323481

Modern circuits often contain standard cells of different threshold voltages (multi-VTs) to achieve a better trade-off between timing and power consumption. Due to the heterogeneous cell structures, the multi-VTs cells impose various implant layer constraints, further complicating the already time-consuming filler cell insertion process. In this paper, we present a fast and near-optimal algorithm to solve the filler insertion problem with complex implant layer rules and minimum filler width constraints. We first propose an inference-driven detecting algorithm to identify each design rule violation accurately. Then, a dynamic-programming-based insertion method is developed to reduce the implant layer violations. Finally, we design a contour-driven violation refinement strategy to further improve manufacturability. Experimental results show that our algorithm can reduce the number of violations significantly compared with state-of-the-art works. Besides, with our identifier in the legalization stage, we can avoid conflicts in advance and solve almost all violations after filler insertion in industrial cases.

关键词： filler insertion

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Modeling of CMOS Transistors from 0.18μm Process by Artificial Neural Network

Modeling of CMOS Transistors from 0.18μm Process by Artific...

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2021 China Semiconductor Technology International Conference, CSTIC 2021

作者： Wei, JiaHao. Zhao, Tian. Zhang, Zheng. Wan, Jing State Key Lab of Asic and System School of Information Science and Engineering Fudan University Shanghai China

ISBN: (纸本)9781665449458

In this work, we developed a new transistor model that can be used to simulate analog circuits. Our model uses ANN to capture the electrical characteristics of transistors instead of the traditional physics-driven model. By preprocessing the transistor data, high-precision modeling is achieved. N-type and p-type transistors with various widths and lengths are fabricated with the 0.18μm analog process in the foundry. ANN modeling on these transistors shows high precision compared with the BSIM3.3 transistor model provided by the foundry. The results show that the DC characteristics of the ANN model are more accurate than the BSIM3.3 transistor model, and have better capture on the on-resistance of the MOSFET. © 2021 IEEE.

关键词： Transistors

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