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7th IEEE Asian Solid-state Circuits Conference, A-SSCC 2011

作者： Yu, Bei Chen, Chixiao Zhu, Yu Zhang, Peng Zhang, Yiwen Zhu, Xiaoshi Ye, Fan Ren, Junyan State Key Laboratory of ASIC and System Fudan University Shanghai China Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University Shanghai China

ISBN: (纸本)9781467303989

A 14-bit 200-MS/s time-interleaved analog-to-digital converter (TI-ADC) is presented. An adaptively-controlled sampling switch is proposed to correct the sample-time error between two interleaved channels and an auto-correlation-based sample-time error detection algorithm is introduced to detect the sample-time error. A prototype ADC is fabricated in a 0.18-μm mixed-signal CMOS process with a power consumption of 460 mW from a 1.8-V supply. The ADC achieves an SNDR of 68.5 dB and an SFDR of 88.5 dB for a 15.33MHz input. © 2011 IEEE.

关键词： Error detection

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A 0.13-μm CMOS 0.8-10.6GHz low noise amplifier with active balun for multi-standard applications

A 0.13-μm CMOS 0.8-10.6GHz low noise amplifier with active ...

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3rd IEEE Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2011

作者： Zhang, Kaichen Li, Wei Ye, Fan Li, Ning Ren, Junyan State Key Laboratory of ASIC and System Fudan University Shanghai China Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University Shanghai China

ISBN: (纸本)9781457716096

A CMOS 0.8-10.6GHz Low Noise Amplifier (LNA) with an active balun is proposed for multi-standard applications. A resistive negative feedback stage is adopted for wideband input impedance matching and an active balun is proposed to realize single-to-differential (S2D) conversion. This LNA was designed in a 0.13-μm RF CMOS process with an active area of 0.33mm2. The post simulation results show that the balun-LNA achieves a minimum NF of 2.8 dB, S11 less than -10 dB, a maximum gain of 16.3 dB and a maximum IIP3 of -3.2 dBm with a power consumption of 13.7 mW from 1.2-V supply. © 2011 IEEE.

关键词： Low noise amplifiers

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A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application

A 4-channel 8-bit 650-MSample/s DAC with interpolation filte...

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2011 IEEE 9th International Conference on asic, asicON 2011

作者： Ha, Qianqian Ye, Fan Chen, Chixiao Zhu, Xiaoshi Wang, Mingshuo Lin, Yujing Li, Ning Ren, Junyan State Key Laboratory of ASIC and System Fudan University Shanghai 201203 China Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University Shanghai 201203 China

ISBN: (纸本)9781612841908

This paper presents a 4-channel 8-bit 6-2 segmented current-steering digital-to-analog converter implemented in 0.13μm CMOS process. For the consideration of embedded application two-times interpolation filter with 4 channels' parallel inputs is added to the DAC input block. Besides, the DAC system is also optimized for a good high-frequency performance. An improved swing reduction circuit is proposed to decrease the digital signal feed-through to the output. The double centroid current array layout is also used to avoid systemic and graded errors. The measured results show that the DAC achieves over 50dB SFDR at 61MHz input and over 41dB at Nyquist input under a sampling rate of 650MS/s at power consumption of 18mW from a 1.2 V power supply. © 2011 IEEE.

关键词： Bandpass filters

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Memory efficient LDPC decoder design

Memory efficient LDPC decoder design

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Yuan Yao Wei Liang Fan Ye Junyan Ren State Key Laboratory of ASIC and System Fudan University Shanghai China State Key Laboratory of ASIC and System and Micro-/NanoElectronics Science and Technology Innovation Platform Fudan University Shanghai China

Hardware complexity of LDPC decoders, which is caused by storage and processing of massive information, is the major reason that encumbers LDPC codes from widely application. Reducing the quantization word length of decoding information can effectively decrease the hardware complexity. But for the absolute value of information keeps increasing during decoding, short word length with finite quantization ranges will lead to serious saturation errors and damage decoding performance. Two quantization schemes is proposed in this paper to reduce the number of memory bits required by decoder design by using short word length while guarantee bit-error-rate (BER) performance. Results shows that these two quantization schemes can simplify the hardware complexity with very little loss of decoding performance.

关键词： Quantization Decoding Iterative decoding Bit error rate Complexity theory Hardware

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A 0.13-μm CMOS 0.8–10.6GHz low noise amplifier with active balun for multi-standard applications

A 0.13-μm CMOS 0.8–10.6GHz low noise amplifier with active...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Kaichen Zhang Wei Li Fan Ye Ning Li Junyan Ren State Key Laboratory of ASIC and System Fudan University Shanghai China Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University Shanghai China

A CMOS 0.8-10.6 GHz Low Noise Amplifier (LNA) with an active balun is proposed for multi-standard applications. A resistive negative feedback stage is adopted for wideband input impedance matching and an active balun is proposed to realize single-to-differential (S2D) conversion. This LNA was designed in a 0.13-μm RF CMOS process with an active area of 0.33 mm 2 . The post simulation results show that the balun-LNA achieves a minimum NF of 2.8 dB, S11 less than -10 dB, a maximum gain of 16.3 dB and a maximum IIP3 of -3.2 dBm with a power consumption of 13.7 mW from 1.2-V supply.

关键词： Impedance matching Gain Wideband Broadband communication Topology CMOS integrated circuits Power demand

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Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching

Nyquist-rate time-interleaved current-steering DAC with dyna...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Long Cheng Fan Ye Hai-Feng Yang Ning Li Jun Xu Jun-Yan Ren State Key Laboratory of ASIC & System Fudan University Shanghai China Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University Shanghai China

A Nyquist-rate time-interleaved current-steering digital-to-analog converter (DAC) with dynamic channel matching (DCM) is proposed. Thanks to the proposed Nyquist- rate time-interleaved architecture, the DAC can properly operate at more than lGS/s for a near-Nyquist output signal. The key limitation of the time-interleaved architecture is the mismatches between channels. The proposed DCM method can be applied to significantly suppress the spurious tones caused by imperfect channel matching. A 14-bit 1 GS/s current-steering DAC with behavior models and a 0.18μm CMOS technology is simulated to illustrate the wideband time-interleaved architecture and the harmonic elimination of the DCM.

关键词： Clocks Linearity Synchronization Switches Digital-analog conversion Arrays

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A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

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Journal of Semiconductors 2010年第6期31卷 109-117页

作者：郑仁亮江旭东姚望杨光尹江伟郑剑钦任俊彦李巍李宁 State Key Laboratory of ASIC and System Fudan University Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is *** transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power *** ESD protected transceiver is fabricated in Jazz Semiconductor＇s 0.18-μm RF CMOS with an area of 6.1 mm^2 and draws a total current of 221 mAfrom 1.8-V *** receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/＋9 *** transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_（1dB） better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 *** hopping time among sub-bands is less than 2.05 ns.

关键词： MB-OFDM UWB transceiver receiver transmitter synthesizer

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A low-spurious fast-hopping MB-OFDM UWB synthesizer

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Journal of Semiconductors 2010年第6期31卷 88-92页

作者：陈丹凤李巍李宁任俊彦 State Key Laboratory of ASIC & System Fudan University Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University

A frequency synthesizer for the ultra-wide band（UWB） group #1 is *** synthesizer uses a phaselocked loop（PLL） and single-sideband（SSB） mixers to generate the three center frequencies of the first band group by mixing 4224 MHz with±264 MHz and 792 MHz,respectively.A novel multi-QSSB mixer is designed to combine the function of frequency selection and frequency conversion for low power and high *** synthesizer is fabricated in Jazz 0.18-μm RF CMOS *** measured reference spur is as low as-69 dBc and the maximum spur is the LO leakage of-32 dBc.A low phase noise of—110 dBc/Hz @ 1 MHz offset and an integrated phase noise of 1.86°are *** hopping time between different bands is less than 1.8 *** synthesizer consumes 30 mA from a 1.8V supply.

关键词： frequency synthesizer SSB mixer VCO PLL

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A new demodulation method with diversity technique used in MB-OFDM UWB system

A new demodulation method with diversity technique used in M...

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2nd Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2010

作者： Su, Wenyan Liu, Liang Ye, Fan Ren, Junyan State Key Laboratory of ASIC and System Micro/Nano-Electronics Science and Technology Innovation Platform Fudan University Shanghai China

ISBN: (纸本)9781424467372

In this paper, we focus on the Dual-Carrier modulation (DCM) technology in the Ultra Wide Band (UWB) wireless communication system. A new demodulation algorithm - getting fully usage of frequency diversity in the UWB channel is proposed. system simulator result shows that the proposed method can get 1.5dB gain at the Per (Packet error) performance of 8% while the data rate is 480Mbps under IEEE CM1 channel. What's more, the method can be implemented by a much fewer complexity hardware architecture, for it avoids LLR calculation in the traditional method.

关键词： Demodulation

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A hardware implementation solution for DC-OFDM-based UWB PHY

A hardware implementation solution for DC-OFDM-based UWB PHY

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IEEE International Conference on Ultra-Wideband

作者： Ye, Fan Ren, Junyan State-Key Lab. of ASIC and System Fudan University Shanghai 201433 China Micro-/Nano-Electronics Science and Technology Innovation Platform Fudan University Shanghai 201433 China

ISBN: (纸本)9781424453061

This paper presents a dual-carrier orthogonal frequency-division multiplexing (DC-OFDM) based ultrawideband (UWB) PHY (RF front-end plus baseband processor) which is compliant with C-WPAN UWB standard. The proposed UWB PHY supports data rates from 53.2 to 480 Mbps, and demonstrates a packet-error-rate (PER) of 8% under multi-path fading, including CM1, CM2, and CM4 channel modes, additive white Gaussian noise (AWGN), and up to 50 ppm carrier frequency offset (CFO) and sampling frequency offset (SFO). It consists of a radio-frequency (RF) transceiver operating in the frequency band group 2 (6204-8844MHz), a 6-bit folding and interpolating analog-to-digital convertors (ADC), a 8-bit current-steering digital-to-analog convertor (DAC) and a digital baseband processor. The front-end circuits have been fabricated using 0.13μm CMOS technology. The digital baseband processor has been implemented on a Xilinx Vertex-5 FPGA platform. © 2010 IEEE.

关键词： Orthogonal frequency division multiplexing

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