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Novel orthogonal modulation format DRZ-FSK/DPSK for high-speed long-haul optical communication

Chinese Optics Letters 2010年第9期8卷 852-855页

作者：张俊文邵宇丰方武良黄博陶理朱江波迟楠 State Key Lab of ASIC & System Department of Communication Science and Engineering Fudan University

We propose a novel advanced orthogonal modulation format dark return-to-zero frequency shift keying/differential phase shift keying （DRZ-FSK/DPSK） and its realization scheme. The DRZ-FSK/DPSK is generated by the combination of a 40-Gb/s return-to-zero （RZ） signal and a DRZ signal which is converted from the RZ using a semiconductor optical amplifier （SOA） based on nonlinear cross polarization rotation （XPR） and then re-modulated by high-bit-rate DPSK at 40 Gb/s. The feasibility of the scheme is exper-imentally demonstrated. Bit error rate （BER） results of the total 80-Gb/s DRZ-FSK/DPSK orthogonal modulation signal with a subsequent 100-km single-mode fiber （SMF） transmission link show its potential for future high-speed long-haul optical communication.

关键词： Bit error rate Light amplifiers Modulation Phase shift keying

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A High Energy-Efficient Reconfigurable VLIW Symmetric Cryptographic Processor with Loop Buffer Structure and Chain Processing Mechanism

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Chinese Journal of Electronics 2017年第6期26卷 1161-1167页

作者： LI Wei ZENG Xiaoyang DAI Zibin NAN Longmei CHEN Tao MA Chao State Key Lab of ASIC and System Fudan University Institute of Information Science and Technology Zhengzhou

By exploring symmetric cryptographic data level and instruction-level parallelism, the reconfigurable processor architecture for symmetric ciphers is presented based on Very-long instruction word(VLIW) structure. The application-specific instruction-set system for symmetric ciphers is proposed. As for the same arithmetic operation of symmetric ciphers, eleven kinds of reconfigurable cryptographic arithmetic units are designed by the reconfigurable technology. As to the requirement of high energy-efficient design, the loop buffer structure for instruction fetching unit is proposed to reduce the power consumption significantly with the same frequency as conventional, meanwhile, the chain processing mechanism is proposed to improve the cryptographic throughput without any area overhead. It has been fabricated with 0.18μm CMOS technology. The result shows that the processor can work up to 200 MHz, and the fourteen kinds of cryptographic algorithms were mapped in the processor, the encryption throughput of AES, SNOW2.0 and SHA2 algorithm can achieve 1.19 Gbps, 1.05 Gbps, and 407 Mbps respectively.

关键词： Symmetric cipher Energy-efficient VLIW processor Loop buffer structure Chain processing mechanism Reconfigurable

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Polarity-Free Resistive Switching Characteristics of CuxO Films for Non-volatile Memory Applications

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Chinese Physics Letters 2008年第3期25卷 1087-1090页

作者：吕杭炳周鹏傅秀峰尹明宋雅丽唐立汤庭鳌林殷茵 School of Microelectronics and State Key Lab of ASIC & System Fudan University Shanghai 200433

Resistive switching characteristics of CuxO films grown by plasma oxidation process at room temperature are investigated. Both bipolar and unipolar stable resistive switching behaviours are observed and confirmed by repeated current voltage measurements. It is found that the RESET current is dependent on SET compliance current. The mechanism behind this new phenomenon can be understood in terms of conductive filaments formation/rupture with the contribution of Joule heating.

关键词： supernova explosion proto-neutron star shock wave

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Patenting Complexity

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IEEE CONSUMER ELECTRONICS MAGAZINE 2014年第4期3卷 75-78页

作者： Corcoran, Peter State Key lab of ASIC and System Fudan University Shanghai China

One of the hallmarks of consumer electronics (CE) products and systems is that, while the product concept is often simple, these products themselves are never simple in their engineering aspects. This short article has only covered three of a much larger number of patents related to the CD drive, and the full engineering details are far more complex and intertwined. But this does serve as a useful example illustrating the complexity and holistic nature of many consumer electronics products.

关键词： Patents Product design Smart phones Product development

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Optimisation of mixed polarity Reed-Muller functions

Journal of Software

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Journal of Software 2013年第11期8卷 2770-2774页

作者： Yang, Meng Lai, Jinmei State Key Lab of ASIC and System Fudan University Shanghai China

This paper presents a genetic algorithm (GA) search method in order to obtain better circuit implementation of the mixed polarity Reed-Muller functions. By combining global searching ability of genetic algorithm and local searching ability of simulated annealing, the proposed GA method could achieve fast convergence. It differs to traditional genetic algorithm, in which the proposed GA forms an intermediate population by using 2/3 population from previous generation and 2/3 population from current generation at the annealing stage. Annealing is then applied to the intermediate population to generate a new population. In the next generation selection, crossover and mutation operations are used for the newly generated population. The calculation of cost function of proposed algorithm is based on parallel tabular technique to overcome the disadvantage of the traditional tabular technique. The results of the tested benchmark indicated that this algorithm is highly effective for searching the best polarity and it could achieve 29% area reduction and 3.68X speedup. © 2013 ACADEMY PUBLISHER.

关键词： Genetic algorithms

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A High-Flexibility and Energy-Efficient Application-Specific Cryptography VLIW Processor for Symmetric Cipher Algorithms 13

A High-Flexibility and Energy-Efficient Application-Specific...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Wei Li Xiaoyang Zeng Longmei Nan Tao Chen Zibin Dai State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

In this paper, a high-flexibility and energy-efficien reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word(VLIW) structure. By analyzing basic operations and storage characteristics of symmetric ciphers, the application-specific instruction-set system for symmetric ciphers is proposed. Eleven kinds of reconfigurable cryptographic arithmetic units are designed to support different operation modes and parameters for symmetric ciphers. It has been fabricated with 0.18μm CMOS technology, the test results show tha the max frequency can reach 200 MHz. Ten kinds of block stream and hash ciphers were mapped in our processor And the encryption throughput of AES, IDEA, Grain128SNOW2.0 and SHA-2 algorithm can achieve 882Mbps449 Mbps, 60 Mbps, 840 Mbps, and 287 Mbps respectively Moreover, the energy efficiency of AES implementation is 0.47 nJ /bit. The result demonstrated that proposed processor outperforms other designs in terms of energy efficiency, throughput and flexibility.

关键词： A High-Flexibility and Energy-Efficient Application-Specific Cryptography VLIW Processor for Symmetric Cipher Algorithms

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Study of DC sputtered SnO growth and its applications in thin film transistors 13

Study of DC sputtered SnO growth and its applications in thi...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Ji-Yu Feng Chun-Feng Hu Xin-Ping Qu State Key lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

In this work, p-type SnO thin films by DC sputtering at low temperature and TFT structures were fabricated. A probable process window of sputtering atmosphere of a mixture of Ar-O was found for SnO TFTs application. Fabricated-type SnO TFTs with I/Iof 5ⅹ103 and mobility of 0.17 cm/V·s on AlO dielectrics were fabricated. An unusual drain current shake in subthreshold field was found and more measurements and analysis should be carried out to explain this phenomenon.

关键词： SnO TFT Study of DC sputtered SnO growth and its applications in thin film transistors

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The Research of Multistage Interconnection Structure Based on Crossbar 13

The Research of Multistage Interconnection Structure Based o...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Haiyuan Ni Wei Li Yingjian Yan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

To realize the high-speed performance of the processor, we need to research an efficient and flexible interconnection structure. In this paper, we propose a multistage interconnect structure based on Crossbar in the Coarse-Grained Reconfigurable Logic Array(CGRLA). Inner internet implements the connection of Functional operation unit flexibly and the outer internet implements the data transmission of different level of function units. Through the simulation verification, the results show that the structure we put up is better than similar design and there are some characteristics, such as small area, low occupancy rate of resources, high flexibility, high area transfer rate and so on, can effectively reduce the routing time in the algorithm implementation process, and improve the processing performance of the processor.

关键词： Interconnection structure Coarse-grained Reconfigurable Logic Array multistage interconnection network small area high flexibility

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The Research of Loop Unrolling for Coarse-Grained Reconfigurable Block Encryption Array 13

The Research of Loop Unrolling for Coarse-Grained Reconfigur...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Yu-Hang Yang Wei Li Jin-Fu Xu Lu Liu State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Coarse-grained reconfigurable block encryption array（REBA） provides massively parallel computing resources but traditional mapping scheme does not develop the advantages of REBA. In this paper, aiming to improve the performance and resource efficiency of algorithm mapping, we research the structure of familiar block cipher algorithm, and propose the speed-up model based on loop unrolling and the modified strategy of unrolling in resource-constrained situation. Experimental results show that the proposed scheme develops the advantage of parallel resources that has 25-55 times higher throughput and 3-11 times higher throughput per unit of array area than the traditional scheme. Compared with other methods, our scheme has a higher performance-area ratio and smaller solving complexity.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Hardware Friendly Stereo Match Refinement Algorithm Using Disparity Gradient Based Region Growth Method 13

A Hardware Friendly Stereo Match Refinement Algorithm Using ...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Hanrui Wang Yize Jin Liming Wang Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Stereo Match is one of the key fields in computer vision. Although many dense two-frame stereo algorithms have been developed in this domain, few utilize cross check and disparity gradient based refinement method. This paper proposes:(1) Cross check method using two generated disparity maps based on left and right original images.(2) A novel occluded and low-texture region growth method based on disparity gradient.(3) Disparity voting method to reduce random error. These practical methods are hardware friendly and can notably improve match accuracy as well as lower the computational and space complexity. The proposed algorithm reaches the highest match accuracy for HR images among existing local methods, attesting to its outstanding effectiveness.

关键词： image A Hardware Friendly Stereo Match Refinement Algorithm Using Disparity Gradient Based Region Growth Method

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