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Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning

IEEE Transactions on Computer-Aided Design of integrated circuits and systems 2025年第3期44卷 1141-1154页

作者： Wu, Zheng Shen, Jinyi Yi, Xiaoling Shang, Li Yang, Fan Zeng, Xuan Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Circuits and Systems Shanghai200433 China KU Leuven Department of Electrical Engineering Microelectronics Circuits and Systems Leuven3000 Belgium Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Computer Science Shanghai200433 China

The design space exploration (DSE) of contemporary microprocessors faces a significant challenge of high-computational cost. In this context, we introduce Prior-boosted graph representation learning (GRL), a novel framework for the DSE of the microarchitectures the microprocessors underpinned by graph embeddings. Using GRL, Prior-boosted GRL constructs a compact and continuous vector space for design representation. This framework is further boosted by an efficient sampling algorithm informed by prior knowledge, which is instrumental in generating a superior set of initial designs to accelerate the exploration process. A well-designed ensemble surrogate model is combined with the multiobjective Bayesian optimization to explore the design space holistically within this graph-embedding domain. Rigorous experimental evaluations conducted on the RISC-V Berkeley-Out-of-Order Machine (BOOM) platform demonstrate that Prior-boosted GRL substantially surpasses preceding methods, achieving a 107.79% enhancement in Pareto front quality compared to the state-of-the-art DSE algorithm. It also outstrips manual designs on performance, power, and area metrics. As of this writing, Prior-boosted GRL holds the first place in the ICCAD 2022 CAD Contest evaluation platform. © 2024 IEEE.

关键词： Graph embeddings

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A Highly Robust integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2025年 13卷 128-133页

作者： Wu, Wanming Chen, Chuanke Zhang, Chunyu Gu, Chen Tang, Yinzhi Wang, Shipeng Yan, Mengwen Tong, Qingding Geng, Di Li, Ling Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China

A highly robust integrated gate driver based on organic thin-film transistors (OTFTs) is proposed that effectively addresses the output degradation caused by depletion-mode operation, instability and variation. The series-connected two-transistor structures and the inverters generate positive gateto- source voltages for internal nodes, which eliminate the leakage current and voltage ripples in depletion-mode operation and extend the support threshold voltage ( V-TH ) range. The simulation waveforms of the 538th stage have no degradation, considering the V-Delta(TH) range from 1.18 to -0.53 V for single-gate (SG) OTFT and that from 2.13 to -8.07 V for dual-gate (DG) OTFT. The fabricated gate drivers generate stable scan signals with almost negligible voltage ripples for SG- and DG-OTFT with V-TH of +7.9 and +1.8 V, respectively. In a 5.8-inch AMOLED panel (resolution: 538x302), the circuit can operate at a frame rate range from 1 to 45 Hz, driven by clocks with a frequency of 12.5 kHz and a swing from 0 to -15 V.

关键词： Gate driver depletion mode depletion mode thin-film transistors thin-film transistors active-matrix displays (AMD) active-matrix displays (AMD) active-matrix displays (AMD)

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TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2025年 13卷 66-72页

作者： Zhao, Yue Xu, Lihua Chen, Chuanke Li, Xufan Shang, Kexin Geng, Di Wang, Lingfei Li, Ling Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China

Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G(1)) bias voltages under the various outer gate (G(2)) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of G(2) significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.

关键词： Field effect transistors Logic gates Electrodes Threshold voltage Fabrication Optimization Three-dimensional displays Modulation Insulators Hafnium oxide Vertical transistor double-surrounding-gate TCAD a-IGZO gate length gate position scaling behavior

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A-31 dBm Sensitivity High-Efficiency RF Energy Harvesting System With Burst Charging Mode for IoT Applications

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IEEE TRANSACTIONS ON circuits AND systems I-REGULAR PAPERS 2025年

作者： Jiang, Haoyu Wu, Zihan Min, Hao Fudan Univ State Key Lab Integrated Chips & Syst Shanghai 201203 Peoples R China Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China

This paper presents a novel high-sensitivity high-efficiency radio frequency (RF) energy harvester with a burst charging technology. The popular high-sensitivity scheme is increasing the number of RF rectifier's stages to output higher voltage which is suitable to supply downstream electronics. This will reduce the input signal amplitude and power conversion efficiency (PCE), which in turn needs more stages and is thus lost in a vicious circle. This paper uses an optimal-stage high-efficiency RF rectifier to solve this problem. A low-frequency (LF) charge pump (CP) is cascaded with the rectifier to raise the DC voltage. To further improve the sensitivity, the system uses a burst charging mode to remove the charge pump's loading effect on the RF rectifier. Measurements demonstrate a -31 dBm sensitivity for 1 V output across a capacitive load in a 55 nm CMOS process technology. The power conversion efficiency equals 31.3% at -25 dBm.

关键词： Rectifiers Radio frequency Sensitivity Voltage Impedance Oscillators Charge pumps Internet of Things circuits Transistors RF energy harvesting CMOS rectifier ultra-low power ultra-high frequency (UHF) wireless power transfer (WPT) charge pump Internet of Things (IoT)

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Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage

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IEEE Access 2025年 13卷 78915-78927页

作者： Wang, Chunshan Ma, Zizhao Zhu, Yuxuan Jin, Chensheng Chen, Dongyu Zhang, Chuxin Chen, Yining Bao, Wenzhong Xie, Yufeng Fudan University State Key Laboratory of Integrated Chips and Systems Shanghai200437 China Zhejiang University School of Integrated Circuits Zizhao Ma Zhejiang Hangzhou311200 China

The process of taking a new semiconductor device from the lab to the factory involves a lot of time, funds and manpower, a large portion of which is spent on device yield improvement. In recent years new methods have been tried to rapidly improve yields and using machine learning (ML) algorithms is one option. However, they usually require a large dataset, which is often unavailable at the device research stage, emerging semiconductors (e.g., 2D materials) are extremely costly to pilot. In this paper, we propose a yield diagnosis and tuning scheme based on ensemble learning and Bayesian optimization, which demonstrate outstanding performance even with a limited data volume. We use real 2-D semiconductor device fabrication process data for scheme evaluation. Experimental results show that the algorithm for yield prediction has achieved regression fitting results whose mean absolute error (MAE) is no more than 8 points and explained variance (EVAR) is no less than 0.62, this indicates that the model fits well on this dataset. We also remanufactured a batch of devices based on the yield tuning recommendations to validate the effectiveness of our approach. The test results indicated a final yield score of 86 points, after evaluating several key indicators such as mobility and hysteresis, resulting in a 62% improvement. © 2013 IEEE.

关键词： Tuning Bayes methods Semiconductor device manufacture Machine learning algorithms Semiconductor device modeling Predictive models Ensemble learning Training Semiconductor device measurement Manufacturing processes

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Effect of Lanthanum-Aluminum Co-Doping on Structure of Hafnium Oxide Ferroelectric Crystals

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ADVANCED SCIENCE 2025年第4期12卷 e2410765页

作者： Li, Zhenhai Tang, Shuqi Wang, Tianyu Liu, Yongkai Meng, Jialin Yu, Jiajie Xu, Kangli Yuan, Ruihong Zhu, Hao Sun, Qingqing Chen, Shiyou Zhang, David Wei Chen, Lin Fudan Univ Sch Microelect State Key Lab Integrated Chips & Syst Shanghai 200433 Peoples R China Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Shandong Univ Sch Integrated Circuits State Key Lab Crystal Mat Jinan 250100 Peoples R China Natl Integrated Circuit Innovat Ctr Shanghai 201203 Peoples R China Shaoxin Lab Shaoxing 312000 Peoples R China

Hafnium oxide (HfO2)-based devices have been extensively evaluated for high-speed and low-power memory applications. Here, the influence of aluminum (Al) and lanthanum (La) co-doping HfO2 thin films on the ferroelectric characteristics of hafnium-based devices is investigated. Among devices with different La/Al ratios, the Al and La co-doped hafnium oxide (HfAlAO) device with 4.2% Al and 2.17% La exhibited the excellent remanent polarization and thermostability. Meanwhile, first principal analyses verified that hafnium-based thin films with 4.2% Al and 2.17% La promoted the formation of the o-phase against the paraelectric phase, providing theoretical support for supporting experimental results. Furthermore, a vertical ferroelectric HfO2 memory based on 3D macaroni architecture is reported. The devices show excellent ferroelectric characteristics of 22 mu C cm-2 under 4.5 MV cm-1 and minimal coercive field of approximate to 1.6 V. In addition, the devices exhibit great memory performance, including the response speed of device can achieve 20 ns and endurance characteristic can achieve 1010 cycles.

关键词： 3D macaroni architecture Al and La co-doping ferroelectricity hafnium-based device high endurance cycles

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Self-Aligned Staggered Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors With Ultra-Low Contact Resistance for High-Speed circuits Application

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2025年 13卷 135-138页

作者： Chen, Chuanke Duan, Xinlv Lu, Congyan Chuai, Xichen Wu, Wanming Zhang, Chunyu Gu, Chen Yang, Guanhua Lu, Nianduan Geng, Di Li, Ling Chinese Acad Sci State Key Lab Fabricat Technol Integrated Circuits Inst Microelect Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China

A self-aligned (SA) staggered structure for amorphous-In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is proposed. The bottom contact between n(+)-IGZO and source/drain (S/D) enables larger contact area and shorter current-transmission distance, thus reducing the contact resistance. The non-overlap structure helps to eliminate the overlap-induced parasitic capacitance, thereby improving the device operating speed. The fabricated SA staggered a-IGZO TFTs exhibit good performance, including channel-width-normalized contact resistance (RCW) as low as 1.53 *** and transit frequency (fT) as high as 1.4 GHz, which are quite competitive in the field of high-speed a-IGZO TFTs.

关键词： Thin film transistors Logic gates Electrodes Contact resistance Sputtering Stress Iron Parasitic capacitance Microelectronics Electron devices a-IGZO TFT parasitic capacitance self-aligned bottom-contact contact resistance transit frequency bias stability

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VirtualN2PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2025年第4期33卷 1004-1013页

作者： Liu, Yiying Yin, Minghui Zhou, Huanhuan You, Yunxia Zhang, Weihua Liu, Hongwei Wang, Chen Zou, Yajie Li, Zhiqiang Chinese Acad Sci Inst Microelect EDA Ctr Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China State Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China

Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.

关键词： Backside power delivery network (BSPDN) interconnects nanosheet FET (NSFET) nanosheet FET (NSFET) process design kit (PDK) process design kit (PDK) ruthenium (Ru) ruthenium (Ru) technology computer-aided design (TCAD) technology computer-aided design (TCAD) wrap-around contact (WAC) wrap-around contact (WAC) wrap-around contact (WAC)

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Effect of recording layer thickness on reducing switching current in double MgO/CoFeB interfaces pMTJ

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JOURNAL OF APPLIED PHYSICS 2025年第11期137卷

作者： Lang, Lili Jiang, Yujie Wang, Cailu Dong, Yemin Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol State Key Lab Mat Integrated Circuits 865 Changning Rd Shanghai 200050 Peoples R China

The effect of the recording layer thickness (t) on the quasi-static switching characteristics in the double MgO/CoFeB interfaces perpendicular magnetic tunnel junctions with the [Co/Pt](n)-based synthetic antiferromagnetic structures has been investigated. It is apparent that the switching current drops rapidly either with slightly increasing the bottom CoFeB thickness (t(CoFeB) >= 1.15 nm) or inserted Ta thickness (t(Ta) >= 0.3 nm), or with marginally decreasing the upper CoFeB thickness (t(CoFeB) <= 0.75 nm), even acquiring a maximum reduction of 41.8%. The tuning mechanism of the write energy dissipation at a specific pulse width can be attributed to two parts. One is an intrinsic leverage of the effective ferromagnetic volume, spontaneous magnetization, and magnetic anisotropy field in the recording layers with a view to their dead layer. The secondary contributors may be closely related to the discrepancy between the resistance-area products of the perpendicular magnetic tunnel junction devices with the six different stack designs. Our results are instructive to the future development of practical ultralow-power chips in binary memory and logical computation fields.

关键词： Magnetic anisotropy

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The Investigation of the Hysteresis and Reliability Mechanism of Amorphous Oxide Semiconductor Thin-Film Transistors Applied in Dynamic Random Access Memory

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2025年第4期72卷 1763-1768页

作者： Luo, Jie Bao, Yunjiao Yang, Yanyu Lu, Yupeng Wang, Guilei Xu, Gaobo Yin, Huaxiang Zhao, Chao Luo, Jun Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China Beijing Superstring Acad Memory Technol Beijing 100176 Peoples R China

In recent years, there has been significant interest in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). Multiple investigations have documented the advancement of AOS TFTs, which are utilized in 2T0C dynamic random access memory (DRAM). This work investigates the hysteresis and reliability performance of InGaZnO (IGZO) TFTs and InSnO (ITO) TFTs under different annealing conditions. ITO TFTs have superior electrical performance, with an extremely little hysteresis of practically zero volts and threshold voltage shifts of less than 0.07 V with negative and positive bias stress (PBS) lasting 1000 s. The analysis of hysteresis relies on considering the traps existing at the interface between the gate dielectric and the channel, the interface between the passivation layer and the channel, and electric dipoles. Meanwhile, the good reliability of ITO TFTs is attributed to the simple composition of the ITO channel and the change in valence state of Sn during annealing. The text discusses the illumination of the influence caused by the shifting of threshold voltage in 2T0C DRAM read transistors. ITO read transistors exhibit a retention duration that is more than seven times longer. This finding indicates that the ITO channel is a potential avenue for research within the realm of 2T0C DRAM.

关键词： Hysteresis InGaZnO (IGZO) thin-film transistor (TFT) InSnO TFT reliability InGaZnO (IGZO) thin-film transistor (TFT) InSnO TFT reliability

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