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A Software/Hardware Co-design Local Irregular Sparsity Method for Accelerating CNNs on FPGA 22

A Software/Hardware Co-design Local Irregular Sparsity Metho...

引用

Workshop Proceedings of the 51st International Conference on Parallel Processing

作者： Jiangwei Shang Zhan Zhang Chuanyou Li Kun Zhang Lei Qian Hongwei Liu Harbin Institute of Technology China Southeast University China State Key Laboratory of Mathematical Engineering and Advanced Computing China

ISBN: (纸本)9781450394451

Convolutional neural networks (CNNs) have been widely used in different areas. The success of CNNs comes with a huge amount of parameters and computations, and nowaday CNNs still keep moving toward larger structures. Although larger structures often bring about better inference accuracy, the increasing size also slows the inference speed down. Recently, various parameter sparsity methods have been proposed to accelerate CNNs by reducing the number of parameters and computations. Existing sparsity methods could be classified into two categories: unstructured and structured. Unstructured sparsity methods easily cause irregularity and thus have a suboptimal speedup. On the other hand, the structured sparsity methods could keep regularity by pruning the parameters following a certain pattern but result in low sparsity. In this paper, we propose a software/hardware co-design approach to bring local irregular sparsity into CNNs. Benefiting from the local irregularity, we design a row-wise computing engine, RConv Engine, to achieve workload balance and remarkable speedup. The experimental results show that our software/hardware co-design method can achieve a 10.9x speedup than the state-of-the-art methods with a negligible accuracy loss.

关键词： field-programmable gate arrays (FPGAs) hardware accelerator convolutional neural network software/hardware co-design sparsity method

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An Extraction Method of Network Security Situation Elements Based on Gradient Lifting Decision Tree

An Extraction Method of Network Security Situation Elements ...

引用

advanced computing and Endogenous Security, International Conference on

作者： Zhaorui Ma Shicheng Zhang Yiheng Chang Qinglei Zhou Xinhao Hu Xia Li State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou China Zhengzhou University of Light Industry Zhengzhou China

ISBN: (纸本)9781665424509

The primary purpose of acquiring network security situation elements is to detect and discover potential security threats from discrete and isolated data. In the complex network environment, the existing network security situation element acquisition technology has the problems of low extraction accuracy and low extraction efficiency. To solve these problems, a method for extracting network security situation elements based on Gradient Boosting Decision Tree (GBDT) is proposed. This method uses the attribute reduction function of rough set to preprocess the original data, which can effectively reduce redundancy. Furthermore, the initial parameters of GBDT are optimized by quantum particle swarm optimization (QPSO) algorithm to improve stability. Finally, the optimized GBDT classifier is used to classify and train with the reduced data set, and the accuracy of the final classifier is continuously improved by reducing the deviation via iterative optimization. Experiments demonstrate that the proposed algorithm achieves significant results and outperforms several state-of-the-art algorithms to the extraction of network security situation elements on the UNSW-NB15 dataset.

关键词： Termination of employment Rough sets Complex networks Network security Stability analysis Classification algorithms Decision trees

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An object based software tool for software measurement

An object based software tool for software measurement

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International Conference on Information Communication and Embedded Systems (ICICES)

作者： G. Santhoshini K. Anbazhagan Zhengzhou Information Science and Technology Institute The State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou Henan China

Software metrics are vital tools to enhance the quality of computer software, and to help in the control of software projects. Object-oriented technology is a new promising approach for developing software systems to reduce software costs and to improve software productivity. Object-oriented metrics is a quantitative measure of the degree to which the software-system or component or process possess the given attribute. From the earliest days of the software engineering discipline there has been wide agreement of the need to measure software processes and products as a pre-condition for establishing control over development activities. Developing modules in a multi-suite environment would result in the problem of integration into a project. Software metrics are useful techniques to avoid this problem. The existing tools are not free of cost. The proposed project is to extract a general subset of these metrics for an object-oriented software development project and is to be of free of cost.

关键词： Complexity theory Software Couplings Software metrics Educational institutions

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A Survey of Automatic Text Summarization Technology Based on Deep Learning

A Survey of Automatic Text Summarization Technology Based on...

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Artificial Intelligence and Computer engineering (ICAICE), International Conference on

作者： Mengli Zhang Gang Zhou Wanting Yu Wenfen Liu State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou China Guilin University of Electronic Technology Guilin China

ISBN: (数字)9781728191461

ISBN: (纸本)9781728191478

With the rapid development of the Internet, the amount of network text data is increasing day by day. It is increasingly becoming a challenge to quickly mine useful information from massive amounts of text data. The emergence of automatic summarization technology provides new ideas and methods for solving this problem. Compared with extractive summarization model, abstractive summarization model more closely resembles the process of human summarization, giving it important research significance. In recent years, with the development of deep learning methods, text summarization technology based on deep learning has made unprecedented breakthroughs. Based on the current mainstream sequence-to- sequence framework, we summarize the state-of-the-art abstractive summarization models, compare the advantages of different models and applicable scenarios, and provide a clear context for researchers in related fields. Furthermore, we also make statistics on the Chinese and English datasets. Finally, we put forward some thoughts on the common problems in the field of automatic text summarization.

关键词： Deep learning Semantics Reinforcement learning Information retrieval Internet Task analysis Context modeling

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SpTFS: Sparse Tensor Format Selection for MTTKRP via Deep Learning 20

SpTFS: Sparse Tensor Format Selection for MTTKRP via Deep Le...

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Supercomputing Conference

作者： Qingxiao Sun Yi Liu Ming Dun Hailong Yang Zhongzhi Luan Lin Gan Guangwen Yang Depei Qian Beihang University China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi China Tsinghua University China

ISBN: (数字)9781728199986

ISBN: (纸本)9781728199993

Canonical polyadic decomposition (CPD) is one of the most common tensor computations adopted in many scientific applications. The major bottleneck of CPD is matricized tensor times Khatri-Rao product (MTTKRP). To optimize the performance of MTTKRP, various sparse tensor formats have been proposed such as CSF and HiCOO. However, due to the spatial complexity of the tensors, no single format fits all tensors. To address this problem, we propose SpTFS, a framework that automatically predicts the optimal storage format for an input sparse tensor. Specifically, SpTFS leverages a set of sampling methods to lower the sparse tensor to fix-sized matrices and specific features. Then, TnsNet combines CNN and the feature layer to accurately predict the optimal format. The experimental results show that SpTFS achieves prediction accuracy of 92.7% and 96% on CPU and GPU respectively.

关键词： Tensors High performance computing Neural networks Graphics processing units Sampling methods Sparse matrices Matrix decomposition

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A Hierarchically Collaborative Ant Colony Based Assembly Algorithm for Security Protocol

A Hierarchically Collaborative Ant Colony Based Assembly Alg...

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2019 International Conference on Wireless Communication, Network and Multimedia engineering(WCNME 2019)

作者： Zhuo Yi Muming Sun Lifeng Cao Xuehui Du State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou Institute of Information Science and Technology Troop 78123 PLA

Assembly of reconfigurable security protocol remains a major challenge for deploying higher security-level but more complicated security strategies in access points with limited resources and computing abilities. To handle this problem commendably, a hierarchically collaborative ant colony-based assembly algorithm was proposed. This algorithm decomposed the security protocol assembly problem into assembling directions controlling sub-task and cryptographic components selection sub-task. Directions control generated assembly subgoals and cryptographic components selection schedules the bestfitted components for given sub-goals. Both sub-tasks adopted a modified version of ant colony algorithm to fulfil its targets. These two ant colony algorithms generate a candidate optimal solution collaboratively for the assembly problem. And a hierarchical pheromone was defined to reinforce positive behaviors of ant colony. Additionally, a Lévy theory based stochastic gradient algorithm was adopted to verify and reoptimize the optimal solution. Experiment results suggest that the proposed algorithm outperforms baseline algorithms in convergence and performance.

关键词： security protocol assembly collaborative ant colony reconfigurable security protocol space-ground integrated network decision-making

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A MPI-Friendly Efficient Static Binary Translator Based on QEMU

A MPI-Friendly Efficient Static Binary Translator Based on Q...

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International Conference on Computer Science and Mechanical Automation (CSMA)

作者： Shuaibing Lu Jianmin Pang Yaomin Pan Jie Tan Tao Dai State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou China Zhengzhou Science and Technology Institute Zhengzhou China

ISBN: (纸本)9781467391672

While high performance computing (HPC) is flourishing these years, the lack of HPC applications is increasingly serious. Conventional binary translation focused on desktop applications and embedded software, which could not be scaled up to HPC. This paper proposed a novel static binary translator MPI-QEMU aiming at MPI programs, the most commonly used on HPC platforms. Firstly, the efficient dynamic binary translator QEMU was altered to a static binary translator to translate the source binary to target platforms. Secondly, by analysing the symbol table and global offset table, the library function name and address were extracted and jacketed. Finally, the generated codes were linked with corresponding native library functions including MPI to generate the target executive binary. The experiments on NPB and IMB benchmarks show that MPI-QEMU translates the benchmarks successfully and gains dramatically speedup.

关键词： Libraries Benchmark testing Software Electronic mail Registers Generators Emulation

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Thread-aware adaptive prefetcher on multicore systems: Improving the performance for multithreaded workloads

Thread-aware adaptive prefetcher on multicore systems: Impro...

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作者： Liu, Peng Yu, Jiyang Huang, Michael C. College of Information Science and Electronic Engineering Zhejiang University Hangzhou310027 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi214125 China Department of Shannon Lab. Huawei Technologies Co. Ltd. Hangzhou310051 China Department of Electrical and Computer Engineering University of Rochester RochesterNY14627-0231 United States

Most processors employ hardware data prefetching techniques to hide memory access latencies. However, the prefetching requests from different threads on a multicore processor can cause severe interference with prefetching and/or demand requests of others. The data prefetching can lead to significant performance degradation due to shared resource contention on shared memory multicore systems. This article proposes a thread-aware data prefetching mechanism based on low-overhead runtime information to tune prefetching modes and aggressiveness, mitigating the resource contention in the memory system. Our solution has three new components: (1) a self-tuning prefetcher that uses runtime feedback to dynamically adjust data prefetching modes and arguments of each thread, (2) a filtering mechanism that informs the hardware about which prefetching request can cause shared data invalidation and should be discarded, and (3) a limiter thread acceleration mechanism to estimate and accelerate the critical thread which has the longest completion time in the parallel region of execution. On a set of multithreaded parallel benchmarks, our thread-aware data prefetchingmechanism improves the overall performance of 64-core system by 13% over a multimode prefetch baseline system with two-level cache organization and conventional modified, exclusive, shared, and invalid-based directory coherence *** compare our approach with the feedback directed prefetching technique and find that it provides 9% performance improvement on multicore systems, while saving the memory bandwidth consumption.

关键词： Benchmarking

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Restricted Boltzmann Machines and Deep Belief Networks on Sunway Cluster

Restricted Boltzmann Machines and Deep Belief Networks on Su...

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IEEE International Conference on High Performance computing and Communications

作者： Kaida Song Yi Liu Rui Wang Meiting Zhao Ziyu Hao Depei Qian Sino-German Joint Software Institute Beihang University. Beijing China State Key Lab of Mathematical Engineering and Advanced Computing Wuxi China

ISBN: (纸本)9781509042982

Deep learning models have showed great potential in classification and recognition over the last decade. Deep Belief Networks (DBNs) have been applied in visual, voice fields due to their great feature presentation capability. However, there are a vast number of time consuming calculations in the training of DBNs. Many researches have accelerated the training of DBNs with good speedups on CPU, GPU, FPGA, etc. At the same time, the latest published Sunway(SW) many-core processor has high computing performance and dedicated heterogeneous architecture. This paper provides a DBNs training system on SW cluster and verifies SW cluster's applicability of training DBNs. We firstly optimize the Restricted Boltzmann Machines and Deep Belief Networks on Sunway processor, then build a parallelism model with linear topology to train DBNs on multiple processors. The system is implemented on the TaihuLight supercomputer and evaluated by training a DBN with 2.8 million parameters with MNIST dataset. Experimental results show that our system achieves considerable speedups on Sunway processors as compared with CPUs.

关键词： Sunway processor TaihuLight supercomputer Restricted Boltzmann Machines Deep Belief Networks data parallelism model

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Using C to implement high-efficient computation of dense optical flow on FPGA-accelerated heterogeneous platforms

Using C to implement high-efficient computation of dense opt...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Zhilei Chai Haojie Zhou Zhibin Wang Dong Wu School of Internet of Things Engineering Jiangnan University Wuxi China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi China

ISBN: (纸本)9781479962464

High-quality algorithms for dense optical flow computation are computationally intensive. To compute them with high speed and low power is vital to make optical flow computation applicable in real-world applications. In contrast to only the Horn-Schunck model being studied on FPGA-based systems today, one of the best linear variational methods for dense optical flow computation, Combine-Brightness-Gradient, is implemented on FPGA-accelerated heterogeneous platforms in this paper. C instead of HDLs is employed and optimizing techniques based on the algorithmic parallelism and hardware architecture are introduced. Experimental results show that 30-110x improvement of the computing efficiency over CPUs was achieved. The FPGA-accelerated version is able to process 640 × 480 image at 12 fps with 0.38 J per frame, while it is 0.8 fps and around 40 J on CPUs. Through demonstrating high performance and low power of dense optical flow algorithm on FPGA-based heterogeneous platforms implemented in C, this paper shows that the off-the-shelf commodity FPGAs coupled with High-Level-Synthesis (HLS) tools could provide an available option when computational efficiency together with development speed are required.

关键词： Optical imaging Optical computing Nonlinear optics Field programmable gate arrays Parallel processing Computer vision Computational modeling

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