This paper focuses on synchronization of radio frequency identification (RFID) reader receivers, which plays a significant role for stability and efficiency of RFID systems. Performance of RFID reader suffers from a b...
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In this paper, a high-flexibility and energy-efficien reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word(VLIW) structure. By analyzing basic operat...
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ISBN:
(纸本)9781467397209
In this paper, a high-flexibility and energy-efficien reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word(VLIW) structure. By analyzing basic operations and storage characteristics of symmetric ciphers, the application-specific instruction-set system for symmetric ciphers is proposed. Eleven kinds of reconfigurable cryptographic arithmetic units are designed to support different operation modes and parameters for symmetric ciphers. It has been fabricated with 0.18μm CMOS technology, the test results show tha the max frequency can reach 200 MHz. Ten kinds of block stream and hash ciphers were mapped in our processor And the encryption throughput of AES, IDEA, Grain128SNOW2.0 and SHA-2 algorithm can achieve 882Mbps449 Mbps, 60 Mbps, 840 Mbps, and 287 Mbps respectively Moreover, the energy efficiency of AES implementation is 0.47 nJ /bit. The result demonstrated that proposed processor outperforms other designs in terms of energy efficiency, throughput and flexibility.
The 44 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 44 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2...
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A 900MHz CMOS PLL using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented. The charge-pump current is insensitive to the changes of temperature and power supply. T...
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A 0.9V high performance 3GHz charge pump phase-locked loop (CP PLL) has been designed in TSMC 28nm CMOS technology, which features high accuracy charge pump (CP) and low phase noise LC voltage-controlled oscillator (L...
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In this work, p-type SnO thin films by DC sputtering at low temperature and TFT structures were fabricated. A probable process window of sputtering atmosphere of a mixture of Ar-O was found for SnO TFTs application. F...
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ISBN:
(纸本)9781467397209
In this work, p-type SnO thin films by DC sputtering at low temperature and TFT structures were fabricated. A probable process window of sputtering atmosphere of a mixture of Ar-O was found for SnO TFTs application. Fabricated-type SnO TFTs with I/Iof 5ⅹ103 and mobility of 0.17 cm/V·s on AlO dielectrics were fabricated. An unusual drain current shake in subthreshold field was found and more measurements and analysis should be carried out to explain this phenomenon.
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited numbe...
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A 6-Gb/s half rate current mode logic (CML) transmitter has been designed in TSMC 28nm CMOS technology, which employs a 3-tap 3-bit feed forward equalizer (FFE), an analog duty cycle correction module (DCC) for half r...
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4 or 8-point IDCT are widely used in traditional video coding standards. However larger size (16/32-point) IDCT has been proposed in the next generation video standard such as HEVC. To fulfill this requirement, this w...
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To realize the high-speed performance of the processor, we need to research an efficient and flexible interconnection structure. In this paper, we propose a multistage interconnect structure based on Crossbar in the C...
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ISBN:
(纸本)9781467397209
To realize the high-speed performance of the processor, we need to research an efficient and flexible interconnection structure. In this paper, we propose a multistage interconnect structure based on Crossbar in the Coarse-Grained Reconfigurable Logic Array(CGRLA). Inner internet implements the connection of Functional operation unit flexibly and the outer internet implements the data transmission of different level of function units. Through the simulation verification, the results show that the structure we put up is better than similar design and there are some characteristics, such as small area, low occupancy rate of resources, high flexibility, high area transfer rate and so on, can effectively reduce the routing time in the algorithm implementation process, and improve the processing performance of the processor.
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