Coarse-grained reconfigurable block encryption array（REBA） provides massively parallel computing resources but traditional mapping scheme does not develop the advantages of REBA. In this paper, aiming to improve the...
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ISBN:
(纸本)9781467397209
Coarse-grained reconfigurable block encryption array（REBA） provides massively parallel computing resources but traditional mapping scheme does not develop the advantages of REBA. In this paper, aiming to improve the performance and resource efficiency of algorithm mapping, we research the structure of familiar block cipher algorithm, and propose the speed-up model based on loop unrolling and the modified strategy of unrolling in resource-constrained situation. Experimental results show that the proposed scheme develops the advantage of parallel resources that has 25-55 times higher throughput and 3-11 times higher throughput per unit of array area than the traditional scheme. Compared with other methods, our scheme has a higher performance-area ratio and smaller solving complexity.
Stereo Match is one of the key fields in computer vision. Although many dense two-frame stereo algorithms have been developed in this domain, few utilize cross check and disparity gradient based refinement method. Thi...
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ISBN:
(纸本)9781467397209
Stereo Match is one of the key fields in computer vision. Although many dense two-frame stereo algorithms have been developed in this domain, few utilize cross check and disparity gradient based refinement method. This paper proposes:(1) Cross check method using two generated disparity maps based on left and right original images.(2) A novel occluded and low-texture region growth method based on disparity gradient.(3) Disparity voting method to reduce random error. These practical methods are hardware friendly and can notably improve match accuracy as well as lower the computational and space complexity. The proposed algorithm reaches the highest match accuracy for HR images among existing local methods, attesting to its outstanding effectiveness.
An optimum design of Decision Feedback Equalizer (DFE) used in Ethernet is *** paper proposes two improving measures for physical implementation—the hybrid form and the coefficient updating unit *** to the results of...
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ISBN:
(纸本)0780392108
An optimum design of Decision Feedback Equalizer (DFE) used in Ethernet is *** paper proposes two improving measures for physical implementation—the hybrid form and the coefficient updating unit *** to the results of synthesis using SMIC,0.18μm CMOS process,the speed,area and power consumption of the improved DFE is optimized by 16%,36%and 39%compared with the transposed form implementation.
LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear *** complex data dependency makes it difficult to parallelize the LU *** this paper,an architecture...
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ISBN:
(纸本)9781509066261;9781509066254
LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear *** complex data dependency makes it difficult to parallelize the LU *** this paper,an architecture with an efficient cache for parallel sparse LU decomposition using FPGA is *** proposed architecture is based on the Gilbert-Peierls(GP) *** using the elimination graph,we find the column dependency of the LU *** is thus possible to exploit the *** a dependency table,a simple but efficient cache strategy and its corresponding architecture are *** proposed cache strategy avoids the cache miss and reduces the size of cache used to store all the intermediate data on *** experiment demonstrates that,our design can achieve speedup of 2.85 x-10.27 x,compared with UMFPACK running on general purpose *** cache size can be reduced by 50.93% on average with the proposed cache strategy.
This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library,...
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Generally, the organic ferroelectric P(VDF-TrFE) thin film is partially crystallized with a mixture of ferroelectric crystallites, non-crystalline molecules, and additional non-ferroelectric crystallites, e.g., Triflu...
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Power amplifier drivers for software-define radio (SDR) transmitter with large gain tuning range are presented. The drivers can work with WCDMA/GSM protocol. Dynamic power control method is adopted to increase the eff...
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This paper proposes a very low-cost VLSI implementation of AES algorithm. This design splits the 128bit computation in every round into four 32bit calculations and exploits 2-level pipeline to finish the process. More...
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A novel two stage wakeup unit is proposed for Semi-passive temperature logger tag based on ISO 18000-6c Rev1 air interface protocol for RFID tags. This wakeup unit assists the tag to realize a temperature log1 functio...
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The design of 1.25Gb/s low jitter frequency-aided dual-loop CMOS clock and data recovery circuit (CDR) applied in SerDes (Serializer&Deserializer) transceiver for Gigabit Ethernet is described. The FLL circuit is ...
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