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30th Great Lakes Symposium on VLSI, GLSVLSI 2020

作者： Fu, Rongliang Zhang, Zhi-Min Tang, Guang-Ming Huang, Junying Ye, Xiao-Chun Fan, Dong-Rui Sun, Ning-Hui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450379441

The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot be directly applied to RSFQ logic due to their distinct properties. For instance, the RSFQ logic gate can work properly when all its fan-ins have the same logic level. This paper presents the design flow from RTL to RSFQ logic netlist and schematic. First, we implement logic synthesis for RSFQ logic circuits. It achieves path balancing while minimizing the number of DFFs. In addition, we propose an automatic schematic generator for the RSFQ logic circuits. It converts the synthesized netlist into its equivalent schematic. A layer assignment algorithm is proposed, which makes all gates layered in the order of the clock arrival time. Experimental results with ISCAS85 and EPFL benchmarks along with some Kogge-Stone adders have shown a 29.2% reduction in the number of DFFs over the breadth-first first search;moreover, 59.57% and 5.3% decrease in the number of layers of the schematic and number of edge crossings over the ELK tool. © 2020 Association for Computing Machinery.

关键词： Logic circuits

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A 1.2 V,3.1%3σ-accuracy thermal sensor analog front-end circuit in 12 nm CMOS process

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Journal of Semiconductors 2021年第3期42卷 54-59页

作者： Liqiong Yang Linfeng Wang Junhua Xiao Longbing Zhang Jian Wang State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China Loongson Technology Corporation Limited Beijing 100095China

This paper presents a 1.2 V high accuracy thermal sensor analog front-end circuit with 7 probes placed around the microprocessor *** analog front-end consists of a BGR(bandgap reference),a DEM(dynamic element matching)control,and *** BGR generates the voltages linear changed with temperature,which are followed by the data read out *** superior accuracy of the BGR’s output voltage is a key factor for sensors fabricated via the FinFET digital ***,a 4-stage folded current bias structure is proposed,to increase DC accuracy and confer immunity against FinFET process variation due to limited device length and low current *** the same time,DEM is also adopted,so as to filter out current branch *** been fabricated via a 12 nm FinFET CMOS process,200 chips were *** measurement results demonstrate that these analog front-end circuits can work steadily below 1.2 V,and a less than 3.1%3σ-accuracy level is *** stability is 0.088 mV/℃across a range from-40 to 130℃.

关键词： CMOS FinFET process microprocessor thermal sensor BGR 4-stage folded

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Research on the Application of Digital Twin in Bridge Rotation Construction

Research on the Application of Digital Twin in Bridge Rotati...

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International Conference on computer Network, Electronic and Automation (ICCNEA)

作者： Yanming Liu Fei Xu Zhenghua Yang Yan Deng Xing Wang State Key Laboratory of Rail Transit Engineering Informatization(FSDI) Xi'an China School of Computer Science and Engineering Xi'an Technological University Xi'an China School of Architecture and Engineering Xi'an Technological University Xi'an China School of Ordnance Science and Technology Xi'an Technological University Xi'an China

With the continuous expansion of China's high-speed railway network, the construction of bridges spanning existing railway lines has become increasingly common. Bridge transition, as a solution for constructing bridges on existing tracks, is crucial for ensuring safety during the construction phase. This research aims to utilize digital twin technology to monitor the construction of bridge transitions and address the limitations of traditional bridge monitoring methods. We employed the Unity3D game engine to create a digital twin virtual scene and facilitated seamless data exchange between the physical and virtual domains using the OPC UA data exchange mechanism. Ultimately, we developed a prototype system for monitoring bridge transition construction. This system effectively monitors critical information and activities during bridge construction, providing early warning capabilities and decision support throughout the construction process. Through the design and implementation of the system prototype, we have confirmed the feasibility of applying digital twin technology in bridge transition construction.

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Communication Lower Bounds of Convolutions in CNNs 20

Communication Lower Bounds of Convolutions in CNNs

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32nd ACM Symposium on Parallelism in Algorithms and architectures, SPAA 2020

作者： Zhang, Xiaoyang Xiao, Junmin Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Science Beijing China

ISBN: (纸本)9781450369350

Convolution is the most time-consuming part in the computation of convolutional neural networks (CNNs). Due to the complex data dependency and the increase in the amount of model samples, the convolution suffers from high overhead on data movement. This work provides comprehensive analysis and methodologies to minimize the communication for the convolutions in CNNs. With an in-depth analysis on the I/O complexity theory under the red-blue pebble game model, we develop a general communication lower bound theory for a composite algorithm which consists of several different sub-computations. Based on the proposed theory, we establish the data movement lower bound results for three main convolution algorithms in CNNs, which are the direct convolution, the image2col method and Winograd algorithm. Furthermore, derived from I/O lower bound results, we design the near communication-optimal strategies respectively for the three main convolution algorithms by fully exploiting the data reuse. The deep analysis demonstrates that our designs are able to nearly reach the minimum communication in a two-level memory hierarchy. © 2020 Owner/Author.

关键词： Convolution

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High Quality Global Routing Algorithm Based on Multi-Stage Optimization

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2024年第4期36卷 607-614页

作者： Genggeng, Liu Zhenyu, Pei Ning, Xu College of Computer and Data Science Fuzhou University Fuzhou350116 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China School of Information Engineering Wuhan University of Technology Wuhan430070 China

Global routing is a crucial step in VLSI physical design. To address the problems that the low utilization rate of capacity and easy to fall into local optimum in the existing global routing algorithms, a high-quality global routing algorithm based on multi-stage optimization is proposed. First, the virtual capacity dynamic adjustment strategy is introduced in the pre-connection stage and the routing reorganization stage to improve the utilization rate of capacity. Then, in the routing reorganization stage, the routing subarea adaptive expansion strategy is proposed to narrow the search space and improve the routing efficiency. Finally, the A* algorithm heuristic search is combined with the global search capability of the particle swarm algorithm to avoid the algorithm to choose the shortest path in the routing process, and thus avoid the algorithm to fall into the local optimum. Experimental results comparing with existing global routing algorithms on ISPD benchmark circuits show that the routing results of proposed algorithm reduce the wirelength by 6.0% to 22.8%. © 2024 Institute of Computing Technology. All rights reserved.

关键词： Routing algorithms

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Building Agile Workflow Microservice System for HPC Applications Based on Fast-start OSv

Building Agile Workflow Microservice System for HPC Applicat...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Qiang Hu Lixian Ma En Shao Guangming Tan State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Science Beijing China

ISBN: (纸本)9781665408790

The advances of containers have significantly promoted the development of microservice architecture. This architecture splits a monolithic application into multiple independent components and the container orchestrator manages these components by the container in the cloud environment. The feasibility of deploying high performance computing(HPC) applications as microservices has been proven, but the existing container orchestrator incurs a large performance overhead as there is interference between different containers on the same physical host. In this paper, we design an agile workflow microservice system for HPC applications with fast-start OSv. We consider improving HPC workflow performance from two aspects: single OSv startup time optimization and workflow orchestration optimization. For single OSv startup time optimization, we design a fast-start OSv by analyzing the process of OSv startup and finding an optimization by modifying OSv source code. In this way, we get nearly 50% improvement of startup time. For workflow orchestration optimization, we propose four optimization techniques to speed up the execution of workflow by jointly considering OSv and workflow features, namely: node fusion, node merge, image preload, boot delay. Furthermore, we utilize our fast startup OSv to design an orchestration system for efficiently building an agile HPC workflow microservice by Kubevirt. Our experimental results optimization microservice system reduces the execution time by 30% compared with the original deployment with docker.

关键词： Cloud computing Conferences Buildings Microservice architectures computer architecture Interference Containers

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Deep Reinforcement Agent for Failure-aware Job scheduling in High-Performance Computing

Deep Reinforcement Agent for Failure-aware Job scheduling in...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Kang Yang Rongyu Cao Yueyuan Zhou Jiawei Zhang En Shao Guangming Tan State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665408790

Job scheduling is crucial in high-performance computing (HPC), which is dedicated to deciding when and which jobs are allocated to the system and placing the jobs on which resources, by considering multiple scheduling goals. Along with the incremental of various resources and dazzling deep learning training (DLT) workloads, job failure becomes a quite common issue in HPC, which will affect user satisfaction and cluster utilization. To alleviate the influence of hardware and software errors as much as possible, in this paper, we aim to tackle the problem of failure-aware job scheduling in HPC clusters. Inspired by the success of previous studies of deep reinforcement learning-driven job scheduling, we propose a novel HPC scheduling agent named FARS (Failure-aware RL-based scheduler) by considering the effects of job failures. On the one hand, a neural network is applied to map the information of raw cluster and job states to job placement decisions. On the other hand, to consider the influence of job failure for user satisfaction and cluster utilization, FARS leverages make-span of the entire workload as the training objective. Additionally, effective exploration and experience replay techniques are applied to obtain effectively converged agent. To evaluate the capability of FARS, we design extensive trace-based simulation experiments with the popular DLT workloads. The experimental results show that, compared with the best baseline model, FARS obtains 5.69% improvement of average make-span under different device error rates. Together, our FARS is an ideal candidate for failure-aware job scheduler in HPC clusters.

关键词： Training Deep learning Processor scheduling Error analysis Computational modeling Conferences Neural networks

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Automatic Classification of Plasmodium for Malaria Diagnosis based on Ensemble Neural Network 2020

Automatic Classification of Plasmodium for Malaria Diagnosis...

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2nd International Conference on Intelligent Medicine and Image Processing, IMIP 2020

作者： Shi, Lulin Guan, Zhen Liang, Chunzi You, Haihang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Central South Hospital of Wuhan University Wuhan China

ISBN: (纸本)9781450377799

Malaria is one of the important public health issues of global concern. It is a kind of infectious disease caused by Plasmodium which can endanger human life and health. The examination of Plasmodium blood smear is the main method to diagnose malaria. Applying machine learning method to automatically analyze malaria smear images is very important for rapid diagnosis and surveillance of malaria. However, the existing machine learning methods need further improvement in feature extraction and generalization ability. For this reason, this paper introduces an ensemble neural network to automatically learn more accurate image features and achieve automatic classification of malaria images. In addition, we propose an adaptive threshold control method for cell segmentation, and then put the cell as center to extract images to obtain the training dataset, which solves the noise problem caused by sliding window cutting. And the idea of transfer learning is applied to solve the problem of shortage of training data. We additionally apply the proposed method to malaria image recognition and achieve 94.58% accuracy. The experimental results show that the model has good robustness and generalization ability and provides a valid data processing method for clinical malaria rapid diagnosis application. © 2020 ACM.

关键词： Diseases

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Empirical investigation of stochastic local search for maximum satisfiability

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Frontiers of computer Science 2019年第1期13卷 86-98页

作者： Yi CHU Chuan LUO Shaowei CAI Haihang YOU State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125China State Key Laboratory of Computer Science Institute of SoftwareChinese Academy of SciencesBeijing 100190China

The maximum satisfiability (MAX-SAT)problem is an important NP-hard problem in theory,and has a broad range of applications in *** local search (SLS)is becoming an increasingly popular method for solving ***,a powerful SLS algorithm called CCLS shows efficiency on solving random and crafted MAX-SAT ***,the performance of CCLS on solving industrial MAX-SAT instances lags far *** this paper,we focus on experimentally analyzing the performance of SLS algorithms for solving industrial MAXSAT ***,we conduct experiments to analyze why CCLS performs poor on industrial *** we propose a new strategy called additive BMS (Best from Multiple Selections)to ease the serious *** integrating CCLS and additive BMS,we develop a new SLS algorithm for MAXSAT called CCABMS,and related experiments indicate the efficiency of ***,we experimentally analyze the effectiveness of initialization methods on SLS algorithms for MAX-SAT,and combine an effective initialization method with CCABMS,resulting in an enhanced *** results show that our enhanced algorithm performs better than its state-of-the-art SLS competitors on a large number of industrial MAX-SAT instances.

关键词： empirical investigation stochastic local search maximum satisfiability industrial instances additive BMS

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A mopso based design exploration algorithm for micro-processor with elitist learning strategy 6th

A mopso based design exploration algorithm for micro-process...

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6th International Conference on Artificial Intelligence and Security,ICAIS 2020

作者： Liu, Niangao Zhi, Tian School of Information Science and Technology University of Science and Technology of China Hefei230026 China State Key Laboratory of Computer Architecture ICT CAS Beijing China

ISBN: (纸本)9789811581007

As the continuous development of processor technology, the design space exploration (DSE) has a critical impact on overall performance. However, due to the lack of systematic way, DSE is usually time-consuming and unaccomplished, leaving much of the opportunity unexploited. In this paper, on the basis of particle swarm optimization (PSO), a multi-object optimization algorithm with elitist learning strategy (ELS) is proposed, with which we construct a prediction model for microprocessor design in the purpose of optimizing performance and efficiency. The proposed algorithm is compared with two other multi-object optimization algorithms by three metrics. The experiment conducted shows the proposed algorithm is more efficient and more effective. © Springer Nature Singapore Pte Ltd 2020.

关键词： Particle swarm optimization (PSO)

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