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17th IFIP WG 10.3 International Conference on Network and Parallel Computing, NPC 2020

作者： Di, Zhanyuan Shao, En He, Mujun University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China Chongqing University Chongqing China

ISBN: (纸本)9783030794774

As a lightweight virtualization solution, container technology can provide resource limiting capabilities and can run multiple isolated process sets under a single kernel instance. Multi-tenant preemption leads to competition in computing, storage, and network resources, resulting in degraded computing service performance. Virtualization service migration can provide a solution to the problem of resource shortage in supercomputing systems. However, the resource overhead and delay in the migration process also reduce the efficiency of high-performance computers. To solve this problem, this dissertation proposes a method of container migration and a tool for supporting container migration. Also, this paper optimizes the startup of containers from checkpoints and proposes a multi-container migration strategy, reducing migration time by 30% compared to sequential migration. The migration method in this paper provides valuable experience for service migration in supercomputers and data centers. © 2021, IFIP International Federation for Information Processing.

关键词： Containers

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Degradation analysis and optimization of temperature effect on MEMRISTOR-based Neural Network Accelerators by electro-thermal simulation

Degradation analysis and optimization of temperature effect ...

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2020 International Conference on Electronics, Communications and Information Technology, CECIT 2020

作者： Shang, Mengjun Yin, Longxiang Xu, Ning School of Information Engineering Wuhan University of Technology Wuhan China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Nowadays, memristor-based neural network accelerators have been widely studied due to their outstanding performance in massive parallel vector matrix multiplication. However, the memristor is sensitive to temperature and its on/off state operation window can be seriously degraded by the increasing temperature, which may lead to computation failures in memristor -based NN accelerators. In this work, we establish an electro-thermal simulation platform to evaluate the temperature impact on memristor -based NN accelerators. With this platform, we first investigate the impact on computation accuracy with the temperature increase in different NN layers in the accelerators. We then apply a temperature-aware NN weight mapping scheme to the most temperature-sensitive layer and achieve 28.89% improvement in computation accuracy, which only has 0.06% difference with the improvement achieved by applied the mapping scheme to the whole NN model. This finding can help to simplify the temperature-aware hardware optimization design in memristor-based neural network accelerators and reduce the power consumption. © Published under licence by IOP Publishing Ltd.

关键词： Memristors

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IMPULP:A Hardware Approach for In-Process Memory Protection via User-Level Partitioning

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Journal of computer Science & Technology 2020年第2期35卷 418-432页

作者： Yang-Yang Zhao Ming-Yu Chen Yu-Hang Liu Zong-Hao Yang Xiao-Jing Zhu Zong-Hui Hong Yun-Ge Guo State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518055China

In recent years many security attacks occur when malicious codes abuse in-process memory *** to the increasing complexity,an application program may call third-party code which cannot be controlled by programmers but may contain security *** a result,the users have the risk of suffering information leakage and control flow ***,current solutions like Intel memory protection extensions(MPX)severely degrade performance,while other approaches like Intel memory protection keys(MPK)lack flexibility in dividing security *** this paper,we propose IMPULP,an effective and efficient hardware approach for in-process memory *** rationale of IMPULP is user-level partitioning that user code segments are divided into different security domains according to their instruction addresses,and accessible memory spaces are specified dynamically for each domain via a set of boundary *** instruction related to memory access will be checked according to its security domain and the corresponding boundaries,and illegal in-process memory access of untrusted code segments will be *** can be leveraged to prevent a wide range of in-process memory abuse attacks,such as buffer overflows and memory *** verification,an FPGA prototype based on RISC-V instruction set architecture has been *** present eight tests to verify the effectiveness of IMPULP,including five memory protection function tests,a test to defense typical buffer overflow,a test to defense famous memory leakage attack named Heartbleed,and a test for security *** execute the SPEC CPU2006 benchmark programs to evaluate the efficiency of *** performance overhead of IMPULP is less than 0.2%runtime on average,which is ***,the resource overhead is less than 5.5%for hardware modification of IMPULP.

关键词： in-process isolation memory protection out-of-bounds user-level partitioning

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TileSpMSpV: A Tiled Algorithm for Sparse Matrix-Sparse Vector Multiplication on GPUs 22

TileSpMSpV: A Tiled Algorithm for Sparse Matrix-Sparse Vecto...

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Proceedings of the 51st International Conference on Parallel Processing

作者： Haonan Ji Huimin Song Shibo Lu Zhou Jin Guangming Tan Weifeng Liu Super Scientific Software Laboratory China University of Petroleum-Beijing China China Northeastern University United States of America State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781450397339

Sparse matrix-sparse vector multiplication (SpMSpV) is an important primitive for graph algorithms and machine learning applications. The sparsity of the input and output vectors makes its floating point efficiency in general lower than sparse matrix-vector multiplication (SpMV) and sparse matrix-matrix multiplication (SpGEMM). Existing parallel SpMSpV methods focused on various row- and column-wise storage formats and merging operations. However, the data locality and sparsity pattern of the input matrix and vector are largely ignored. We in this paper propose TileSpMSpV, a tiled algorithm for accelerating SpMSpV on GPUs. Firstly, tile-wise storage structures are developed for fast positioning a group of nonzeros in matrix and vectors. Then, we develop the TileSpMSpV algorithm on top of the storage structures. In addition, to accelerate directional optimization breadth-first search (BFS) by using TileSpMSpV, we propose a TileBFS algorithm including three kernels called Push-CSC, Push-CSR and Pull-CSC. In the experiments running on a high-end NVIDIA GPU and using 2757 sparse matrices, the TileSpMSpV algorithm outperforms TileSpMV, cuSPARSE and CombBLAS by a factor of on average 1.83, 17.18 and 17.20 (up to 7.68, 1050.02 and 235.90), respectively. Moreover, our TileBFS algorithm outperforms Gunrock and GSwitch by a factor of on average 2.88 and 4.52 (up to 21.35 and 1000.85), respectively.

关键词： GPU Sparse matrix BFS Tiling SpMSpV

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OStoreBench: Benchmarking Distributed Object Storage Systems Using Real-World Application Scenarios 3rd

OStoreBench: Benchmarking Distributed Object Storage Systems...

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3rd BenchCouncil International Symposium on Benchmarking, Measuring, and Optimizing, Bench 2020

作者： Kang, Guoxin Kong, Defei Wang, Lei Zhan, Jianfeng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China ByteDance Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783030710576

Their hierarchical organization and metadata management limit the traditional file storage systems’ scalability. The industry widely uses Distributed Object Storage Systems because they keep the advantages of traditional file storage systems, e.g., data sharing, and alleviate the scalability issue through benefiting from the flat namespaces and integrating the meta-data in the object. However, evaluating and comparing distributed object storage systems remains a significant challenge. The existing DOSS benchmarks provide simple read/write operations without considering the complex workload characteristics in request arrival patterns and request size distribution. This paper presents an Object Storage Benchmark suite, named OStoreBench, which characterizes critical paths of three real-world application scenarios, including online service, big data analysis, and file backup. We evaluate three state-of-the-practice object storage systems using OStoreBench, including Ceph, Openstack Swift, and Haystack. The benchmark suite is publicly available from https://***/EVERYGO111/OStoreBench. © 2021, Springer Nature Switzerland AG.

关键词： Metadata

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AutoQNN: An End-to-End Framework for Automatically Quantizing Neural Networks

arXiv

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arXiv 2023年

作者： Gong, Cheng Lu, Ye Dai, Surong Qian, Deng Du, Chenkun Li, Tao College of Software Nankai University Tianjin300350 China College of Computer Science Nankai University Tianjin300350 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China

Exploring the expected quantizing scheme with suitable mixed-precision policy is the key point to compress deep neural networks (DNNs) in high efficiency and accuracy. This exploration implies heavy workloads for domain experts, and an automatic compression method is needed. However, the huge search space of the automatic method introduces plenty of computing budgets that make the automatic process challenging to be applied in real scenarios. In this paper, we propose an end-to-end framework named AutoQNN, for automatically quantizing different layers utilizing different schemes and bitwidths without any human labor. AutoQNN can seek desirable quantizing schemes and mixed-precision policies for mainstream DNN models efficiently by involving three techniques: quantizing scheme search (QSS), quantizing precision learning (QPL), and quantized architecture generation (QAG). QSS introduces five quantizing schemes and defines three new schemes as a candidate set for scheme search, and then uses the differentiable neural architecture search (DNAS) algorithm to seek the layer- or model-desired scheme from the set. QPL is the first method to learn mixed-precision policies by reparameterizing the bitwidths of quantizing schemes, to the best of our knowledge. QPL optimizes both classification loss and precision loss of DNNs efficiently and obtains the relatively optimal mixed-precision model within limited model size and memory footprint. QAG is designed to convert arbitrary architectures into corresponding quantized ones without manual intervention, to facilitate end-to-end neural network quantization. We have implemented AutoQNN and integrated it into Keras. Extensive experiments demonstrate that AutoQNN can consistently outperform state-of-the-art quantization. For 2-bit weight and activation of AlexNet and ResNet18, AutoQNN can achieve the accuracy results of 59.75% and 68.86%, respectively, and obtain accuracy improvements by up to 1.65% and 1.74%, respectively, compared

关键词： Deep neural networks

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Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization 21

Network-on-Interposer Design for Agile Neural-Network Proces...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Mengdi Wang Ying Wang Cheng Liu Lei Zhang Institute of Computing Technology Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences and State Key Laboratory of Computer Architecture

ISBN: (纸本)9781665432740

Chiplet based multi-die integration has been thought as a key enabler of the agile chip development flow. For 2.5D based multi-die system, Network on Interposer plays an essential role in the performance and the development cost of the chips. This work proposed a reusable NoI design for agile AI chip customization. The proposed NoI design can self-adapt to the inter-die communication patterns of various neural network applications, so the produced interposers can be reused across different AI chip specifications. Experimental results show the proposed NoI design brings 42.7%~79.5% of total data communication latency reduction in different scenarios, and it also decreased the area overhead by 26.4%.

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LACC:a hardware and software co-design accelerator for deep neural networks

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High Technology Letters 2021年第1期27卷 62-67页

作者： Yu Yong Zhi Tian Zhou Shengyuan State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190P.R.China School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049P.R.China Cambricon Technologies Ltd Beijing 100190P.R.China

With the increasing of data size and model size,deep neural networks(DNNs)show outstanding performance in many artificial intelligence(AI)*** the big model size makes it a challenge for high-performance and low-power running DNN on processors,such as central processing unit(CPU),graphics processing unit(GPU),and tensor processing unit(TPU).This paper proposes a LOGNN data representation of 8 bits and a hardware and software co-design deep neural network accelerator LACC to meet the *** data representation replaces multiply operations to add and shift operations in running *** accelerator achieves higher efficiency than the state-of-the-art DNN accelerators by domain specific arithmetic computing ***,LACC speeds up the performance per watt by 1.5 times,compared to the state-of-the-art DNN accelerators on average.

关键词： deep neural network(DNN) domain specific accelerator domain specific data type

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KOP-Fuzzer: A key-Operation-based Fuzzer for Type Confusion Bugs in JavaScript Engines

KOP-Fuzzer: A Key-Operation-based Fuzzer for Type Confusion ...

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IEEE Annual International computer Software and Applications Conference (COMPSAC)

作者： Lili Sun Chenggang Wu Zhe Wang Yan Kang Bowen Tang State Key Laboratory of Computer Architecture Chinese Academy of Sciences Institute of Computing Technology University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9781665488105

ISBN: (纸本)9781665488112

JavaScript (JS) engines are a core component of a lot of software, such as web browsers, PDF readers and flash players. There has been much research on finding JS engine vulnerabilities. However, due to the fact that a JS engine's input space is infinite and the vulnerability triggering conditions are extremely strict, it is difficult to generate test cases that are able to trigger deep logic errors in fuzzing. This paper aims to explore an approach which incorporates the human experience into fuzzing. We propose a key-Operation-based Fuzzer (KOP-Fuzzer), to explore the type confusion vulnerabilities in JS engines. Based on human knowledge, we summarize a trigger model and extract key operations for type confusion vulnerabilities in JS engines. We use clustering to extract the key-operation methods from the engine's source code and develop a fuzzing system for key -operation mutation. Our experimental results demonstrate that the KOP-Fuzzer generates valid test cases with 1.5x fewer runtime errors, while also improving the edge coverage (2.082 %) and key-operation coverage (6.452 %), when compared with the state-of-the-art JS engine fuzzers. The KOP-Fuzzer discovered a total of 21 new bugs in ChakraCore and JavaScriptCore, where 16 of them are caused by the engine's incorrect handling of key operations and 5 of them are caused by type confusions.

关键词： Codes Runtime Conferences computer bugs Fuzzing Software Browsers

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Energy-Efficient and Reliable Federated Learning in Heterogeneous Mobile-Edge Computing

Energy-Efficient and Reliable Federated Learning in Heteroge...

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Symposia and Workshops on Ubiquitous, Autonomic and Trusted Computing, UIC-ATC

作者： Yan Xu Liying Li Peijin Cong Junlong Zhou School of Computer Science and Engineering Nanjing University of Science and Technology China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

As a decentralized machine learning paradigm, Federated Learning (FL) is an emerging technique to protect user data privacy in Mobile Edge Computing (MEC). FL adopts the idea of distributed privacy computing, enabling the terminal devices to train machine learning models required by servers locally and upload model parameters to servers for aggregation. However, in the process of coupling FL with MEC systems, device heterogeneity, malicious use of poisoned data by users and limited system resources will seriously affect FL training accuracy, system reliability and energy efficiency. In this paper, a highly reliable and energy-efficient FL scheme is designed to solve these issues. Specifically, we first propose a calculation method for estimating the reliability of heterogeneous devices. Then, we design a highly reliable device selection scheme based on devices’ reliability, computing power, and participation times. Finally, we utilize the slack time in FL training to dynamically adjust the voltage and frequency of devices for reducing the energy consumption of training. Experimental results show that our proposed scheme improves the accuracy by up to 36.45% on average and saves energy by up to 48.63% when compared to the baseline and benchmarking methods.

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