检索结果-内蒙古大学图书馆

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022

作者： Fang, Yuqing Li, Qingxuan Wang, Tianyu Meng, Jialin Sun, QingQing Zhang, David Wei Chen, Lin School of Microelectronics Fudan University State Key Laboratory of Asic and System Shanghai200433 China Zhangjiang Fudan International Innovation Center Shanghai201203 China

ISBN: (数字)9781665492690

ISBN: (纸本)9781665492690

With the development of artificial intelligence technology, the usage of perception, storage and computing integrated devices for neuromorphic computing has become a research hotspot. We have successfully fabricated a photonmemristive device with optical sensing ability, which could simulate the synaptic behaviors in the human brain. The device could receive and respond to ultraviolet light, and realize synaptic functions, such as short-term plasticity, long-term potentiation and paired-pulse facilitation. In addition, it was able to be applied in the image identification field, the recognition rate could reach 92.2%. The device still had high stability and low operating current after light pulses excitation. The two-terminal photonic memristive unit is expected to be integrated into a 3D system and have broad application prospects in the field of artificial intelligence. © 2022 IEEE.

关键词： Memristors

来源：评论

学校读者我要写书评

暂无评论

Compact polarization transformation-enabled on-chip delay line for frequency-swept laser nonlinearity calibration

引用

Optics Express 2025年第11期33卷 22676-22684页

作者： Ke Zhang Guanzhu Zhou Senlin Zhang Rui Zhu Jie Sun Shijin Ding David Wei Zhang State Key Laboratory of ASIC & System School of Microelectronics Fudan University Shanghai 200433 China Silith Technology Co. Ltd. Shanghai 201210 China sjding@*** dwzhang@***

An on-chip optical delay line with low-loss and compact waveguide configurations is a crucial component for functional photonic integrated circuits, such as optical coherence tomography, optical gyroscopes, and frequency-modulated continuous-wave (FMCW) LiDAR systems. In this paper, we proposed a low-loss and compact on-chip delay line structure integrated with a polarization transformation-enabled 2-pass architecture. A total delay of 10.46 ns is achieved using a 0.8-m-long silicon nitride waveguide spiral. The losses of the delay line operating in the TE and TM modes are 0.083 dB/cm and 0.213 dB/cm, respectively. Further, the nonlinearity calibration of the frequency-swept laser is conducted with the assistance of the designed delay line. It is indicated that the calibration method is validated in an FMCW LiDAR system, and a significant enhancement in the signal-to-noise ratio is achieved. This work offers valuable insights into developing highly integrated on-chip FMCW LiDAR systems with an improved linearity of frequency-swept output light.

关键词： Frequency modulation Optical coherence tomography Optical systems Photonic crystals Silicon nitride Waveguide cores

来源：评论

学校读者我要写书评

暂无评论

Sensitive MoS_(2)photodetector cell with high air-stability for multifunctional in-sensor computing

引用

Chip 2022年第3期1卷 61-68页

作者： Dong-Hui Zhao Zheng-Hao Gu Tian-Yu Wang Xiao-Jiao Guo Xi-Xi Jiang Min Zhang Hao Zhu Lin Chen Qing-Qing Sun David Wei Zhang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China Zhangjiang Fudan International Innova-tion Center Shanghai 201203China College of Data Science Jiaxing Univer-sityJiaxing City 314001China

With the development of artificial intelligence and the Internet of Things,the number of sensory nodes is growing rapidly,leading to the exchange of large quantities of redundant data between sensors and computing *** computing schemes,which integrate sensing and processing,have provided a promising route to addressing the sensing/processing bottleneck by reducing power consumption,time delay and hardware *** this study,an in-sensor computing architecture involving a photoelectronic cell based on a wafer-scale two-dimensional MoS_(2)thin film was *** MoS_(2)photodetector cell used a top-gate device structure with in-dium tin oxide(ITO)as the transparent gate electrode,which exhibited high air-stability and a high photoresponsivity(R)up to 555.8 A W^(-1) at an illumination power density(P_(in))of 16.0μW cm^(-2)(λ=500 nm).Additionally,a MoS_(2)photodetector array with uniform photoresponsive characteristics was ***,logic gates,including inverter,NAND,and NOR,were achieved based on MoS_(2)photodetector *** multifunctional and robust in-sensor computing was ascribed to the uniform wafer-scale MoS_(2)film grown by atomic layer deposition(ALD)and the unique device *** the detection of optical signals and logic operations were achieved through MoS_(2)photodetector cells with area efficiency,the proposed in-sensor computing device paves the way for potential applications in high-performance,integrated sensing and processing systems.

关键词： In-sensor computing Photodetectors MoS_(2) Atomic layer de-position Transparent electrode

来源：评论

学校读者我要写书评

暂无评论

High-Performance Placement Engine for Modern Large-Scale FPGAs with Heterogeneity and Clock Constraints

引用

IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2024年第3期43卷 956-969页

作者： Zhu, Ziran Mei, Yangjie Deng, Kangkang He, Huan Chen, Jianli Yang, Jun Chang, Yao-Wen Southeast University National ASIC System Engineering Research Center School of Integrated Circuits Nanjing210096 China Peking University Beijing International Center for Mathematical Research Beijing100871 China Hangzhou Huawei Enterprises Telecommunication Technologies Company Ltd. Central Hardware Planning & Architecture Design Department Hangzhou310000 China Fudan University State Key Laboratory of ASIC and System Shanghai200433 China National Taiwan University Graduate Institute of Electronics Engineering The Department of Electrical Engineering Taipei10617 Taiwan

As field-programmable gate array (FPGA) architectures continue to evolve and become more complex, the heterogeneity and clock constraints imposed by modern FPGAs have posed significant challenges to FPGA placement. This article proposes a high-performance placement engine for modern large-scale FPGAs with heterogeneity and clock constraints. To improve efficiency and scalability, we develop a clustering method considering both internal/external connectivity and the balance of block types to build the hierarchy. In each hierarchy level, we propose a hybrid penalty and augmented Lagrangian method (HPALM) to convert the FPGA global placement with heterogeneity and clock constraints into a series of unconstrained optimization subproblems, then use the Adam method to solve each subproblem. In particular, we prove that the HPALM is globally convergent for global placement. Besides, a matching-based IP block legalization is developed to legalize the DSPs and RAMs, and a multistage packing is presented to cluster LUTs and FFs into HCLBs. Finally, we propose a history-based legalization to legalize CLBs in an FPGA, and a simulated-annealing-based detailed placement is presented to reduce the wirelength while maintaining legality. Compared with the state-of-the-art works, experimental results based on the ISPD 2017 contest benchmarks show that the proposed algorithm can achieve the shortest routed wirelength in a reasonable runtime. © 1982-2012 IEEE.

关键词： Table lookup

来源：评论

学校读者我要写书评

暂无评论

Radar Based Gesture Recognition in Embedded systems 6

Radar Based Gesture Recognition in Embedded Systems

引用

6th International Conference on Electronics Technology, ICET 2023

作者： Liang, Tingxuan Lin, Yue Xu, Hongtao Fudan University State Key Laboratory of Integrated Chips & System Department of Microelectronics Shanghai China R&d ICLegend Micro Nanjing China

ISBN: (纸本)9798350337693

Gesture recognition has played a significant role in human-computer interaction. Millimeter-wave radar sensor is a class of necessary sensor for human gesture recognition in an indoor condition due to its advantages of private protection, low hardware cost. However, for gesture recognition application, it is difficult for us to meet the requirements of high accuracy and real-time simultaneously in embedded system. Unlike other conventional method which increase the cost of hardware of embedded system to improve detection accuracy, in this paper, we proposed a radar-based gesture recognition in low power consumption and low-cost embedded system by using 24 GHz millimeter-wave radar with 1 transmitting antenna and 2 receiving antenna channels. Besides, 2D trajectory information on XY coordination and lightweight deep neural network have been used to distinct ten air-writing numbers. As a result, this system could reconstruct the air-writing symbols and recognize numeric character 0-9 with 95.2% accuracy in real time. © 2023 IEEE.

关键词： Embedded systems

来源：评论

学校读者我要写书评

暂无评论

The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

引用

43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

来源：评论

学校读者我要写书评

暂无评论

Ultrafast flash memory with large self-rectifying ratio based on atomically thin MoS_(2)-channel transistor

引用

Materials Futures 2022年第2期1卷 153-162页

作者： Liwei Liu Yibo Sun Xiaohe Huang Chunsen Liu Zhaowu Tang Senfeng Zeng David Wei Zhang Shaozhi Deng Peng Zhou Frontier Institute of Chip and System Fudan UniversityShanghai 200433People’s Republic of China State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433People’s Republic of China State Key Laboratory of Optoelectronic Materials and Technologies Guangdong Province Key Laboratory of Display Material and TechnologySchool of Electronics and Information TechnologySun Yat-sen UniversityGuangzhou 510275People’s Republic of China

Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big *** addition,the realisation of ultrafast flash memory with novel functions offers a means of combining heterogeneous components into a homogeneous device without considering impedance *** report proposes a 20 ns programme flash memory with 10^(8) self-rectifying ratios based on a 0.65 nm-thick MoS_(2)-channel transistor.A high-quality van der Waals heterojunction with a sharp interface is formed between the Cr/Au metal floating layer and h-BN tunnelling *** addition,the large rectification ratio and low ideality factor(n=1.13)facilitate the application of the MoS_(2)-channel flash memory as a bit-line select ***,owing to the ultralow MoS_(2)/h-BN heterojunction capacitance(50 fF),the memory device exhibits superior performance as a high-frequency(up to 1 MHz)sine signal *** results pave the way toward the potential utilisation of multifunctional memory devices in ultrafast two-dimensional NAND-flash applications.

关键词： ultra-fast flash memory metal floating gate atomic sharp interface atomic thin channel self-rectification transistor high-frequency rectifier

来源：评论

学校读者我要写书评

暂无评论

Band Alignment at the Al2O3/β-Ga2O3 Interface with CHF3 Treatment

引用

Chinese Physics Letters 2020年第7期37卷 92-95页

作者： Hao Liu Wen-Jun Liu Yi-Fan Xiao Chao-Chao Liu Xiao-Han Wu and Shi-Jin Ding State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China

The energy band alignment at the atomic layer deposited Al2O3/β-Ga2O3 interface with CHF3 treatment was characterized by x-ray photoelectron spectroscopy and secondary ion mass spectrometry(SIMS).With additional CHF3 plasma treatment,the conduction band offset increases from 1.95±0.1 eV to 2.32±0.1 eV;and the valence band offset decreases from 0.21±0.1 eV to-0.16±0.1 *** a result,the energy band alignment changes from type I to type *** energy band alignment transition could be attributed to the downshift of the core-level of Ga 3d,resulting from the Ga–F bond formation in the F-rich interfacial layer,which is confirmed by the SIMS results.

关键词： CHF3 SIMS treatment

来源：评论

学校读者我要写书评

暂无评论

A High-Resolution Large Swing Signal Generation Test Method for ADC Automatic Testing

A High-Resolution Large Swing Signal Generation Test Method ...

引用

Electronic Technology and Information Science (ICETIS), International Conference on

作者： Bofu Li Dameng Li Yang Liu Yuanhui Yan Pengcheng Xiao Shunfeng Han Beijing smartchip microelectronics technology company limited Beijing China State Key Laboratory of ASIC & System Fudan University Shanghai China

ISBN: (数字)9798350388343

ISBN: (纸本)9798350388350

In this paper, a hardware design for a high-resolution ADC with large swing based on ADVANTEST V93000 ATE is presented, In order to reduce harmonic distortion, a software based signal generation method without changing hardware circuits has also been proposed. The results of theoretical analysis and test verification show that the signal generation circuit can generate Ramp wave and Sine wave with peak-to-peak value of 29V, with THD better than -103dB and SNR better than 105dB, which can meet the test requirements of ADC with 16bit, ±10 V and even higher input swing.

关键词： Information science Automatic testing Circuits Hardware Software Harmonic distortion Signal resolution

来源：评论

学校读者我要写书评

暂无评论

Combining Max Pooling and ReLU Activation Function in Stochastic Computing 14

Combining Max Pooling and ReLU Activation Function in Stocha...

引用

14th IEEE International Conference on asic, asicON 2021

作者： Li, Lixing Chen, Deyang Xue, Xiaoyong Zeng, Xiaoyang Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai200433 China

ISBN: (纸本)9781665411493

In the convolutional neural networks (CNNs) based on stochastic computing (SC), the design of pooling layer is always a key point. Although some SC-based CNNs have been proposed, the circuit output accuracy of pooling layer is not ideal at present. Besides, the pooling layer takes most of the area and power consumption. In this paper, we propose a new kind of SC ReLU with feedback and a combined scheme of SC ReLU and max pooling. The previous one improves the circuit output accuracy of SC ReLU while the latter one saves nearly 25% of the area and power consumption. © 2021 IEEE.

关键词： Electric power utilization

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：