One of the most promising applications for high temperature superconductors (HTSCs) is for use as signal interconnects between bare integrated circuits (ICs) in multichip modules (MCMs). For HTSC MCM and other related...
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One of the most promising applications for high temperature superconductors (HTSCs) is for use as signal interconnects between bare integrated circuits (ICs) in multichip modules (MCMs). For HTSC MCM and other related electronic applications, it is necessary to fabricate several YBa/sub 2/Cu/sub 3/O/sub 7-x/ (YBCO) layers separated by thick low dielectric layers. In this work, YBCO/yttrium stabilized zirconia (YSZ)/SiO/sub 2//YSZ/YBCO multilayer structures have been successfully deposited with patterned YBCO layers on single-crystal YSZ substrates. A reactive sputtering technique was used to grow the SiO/sub 2/ layer and the ion beam assisted deposition (IBAD) method was used to form biaxially aligned YSZ layers. In contrast to previously reported work, the top YBCO layer did not show any cracking. Using this process, a novel two-layer test vehicle was fabricated. A clock distribution circuit was mounted on the superconducting test vehicle to form a ring oscillator. The functionality of the test vehicle was found to be about 100 MHz.
This paper presents a novel fault tolerant approach for SRAM-based FPGAS. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs an...
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This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs an...
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This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature.
This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed ...
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ISBN:
(纸本)078035012X
This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used. For non-adaptive test, eight programming steps is required to diagnose all the possible faults under the given single fault model. The accuracy of the fault diagnosing is one segment for a segment stuck-at or stuck-open fault, a segment pair for a bridge fault, a switch for switch stuck-on or stuck-off fault.
This paper presents a five-step programming method to diagnose faults in FPGA interconnection resources. A single and a multiple fault model are given. The accuracy of fault location is a single segment for a segment ...
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This paper presents a five-step programming method to diagnose faults in FPGA interconnection resources. A single and a multiple fault model are given. The accuracy of fault location is a single segment for a segment stuck-at fault or a segment open fault, a segment pair or terminal pair for bridge fault or switch stuck-off fault under the single fault assumption. Similar accuracy can be achieved under the multiple fault assumption.
A new algorithm of vector quantization (VQ) suitable for VLSI implementation is proposed. In this algorithm, a large number of codewords will be rejected before computing its MAE while the image quality is maintained....
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A new algorithm of vector quantization (VQ) suitable for VLSI implementation is proposed. In this algorithm, a large number of codewords will be rejected before computing its MAE while the image quality is maintained. A criterion of distortion measure, the presorted codebook, a nearest neighbors search algorithm and a dichotomy search method adopted in the proposed algorithm have resulted in a considerable reduction in the complexity of VLSI implementation.
Partial scan testability design method for sequential circuits with multiple feedback is proposed in this paper. The selection of flip-flops is aimed at breaking up the cyclic structure and reducing the sequential dep...
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ISBN:
(纸本)0780330625
Partial scan testability design method for sequential circuits with multiple feedback is proposed in this paper. The selection of flip-flops is aimed at breaking up the cyclic structure and reducing the sequential depth of the circuit so that test generation can be simplified. Combinational test generation algorithm is used in this method and it can reach ideal fault coverage. Experimental results show that above 90% fault coverage can be obtained by scanning just 20-40% of the flip-flops.
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