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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Cai, Chang Zhao, Kai Yu, Jian Chen, Gengsheng Shen, Mingjie Ning, Bingxu Yu, Jun Fudan University State Key Laboratory of Asic and System Shanghai China Fudan Microelectronics Co. Ltd. Shanghai China Zhangjiang Fudan International Innovation Center China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, the Ring Oscillators (ROs) with inverters, 8 (or 16) dividers, and 3-level buffers are fabricated in a 22 nm Ultra-Thin Body and Buried oxide (UTBB) Fully Depleted Silicon on Insulator (FDSOI) technology. The ROs are comprehensively characterized by reliability tests including the impact of core voltages, temperatures, body bias, and Total Ionizing Dose (TID) effect. The RO frequency shows positive correlation with the increase of core voltage. With the positive variation of temperature conditions, the exponential growth of standby current, linear increase of the working current, and oscillation frequency are investigated in HSPICE simulation and measured by Automatic Test Equipment (ATE). Besides, the phenomenon of leakages for the core current and the Input/ Output (I/O) current are observed owing to the TID effect. Though the TID-induced degradations in frequency are observed, the ROs still have regular working functions. © 2022 IEEE.

关键词： Silicon on insulator technology

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Molten salt synthesis of porous carbon and its application in supercapacitors: A review

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Journal of Energy Chemistry 2021年第10期30卷 622-640,I0016页

作者： Zhongya Pang Guangshi Li Xiaolu Xiong Li Ji Qian Xu Xingli Zou Xionggang Lu State Key Laboratory of Advanced Special Steel&Shanghai Key Laboratory of Advanced Ferrometallurgy&School of Materials Science and Engineering Shanghai University99#Shangda RoadShanghai 200444China State Key Laboratory of ASIC and System School of MicroelectronicsFudan University825#Zhangheng RoadShanghai 200433China

Carbon materials have taken an important role in supercapacitor applications due to their outstanding features of large surface area,low price,and stable physicochemical *** research efforts have been devoted to the development of novel synthesis strategy for the preparation of porous carbon materials in recent *** particular,molten salt strategy represents an emerging and promising method,whereby it has shown great potential in achieving tailored production of porous *** has been proved that the molten salt-assisted production of carbon via the direct carbonization of carbonaceous precursors is an effective ***,with the incorporation of electrochemical technology,molten salt synthesis of porous carbon has become flexible and ***,this review focuses on the mainstream molten salt synthesis strategies for the production of porous carbon materials,which includes direct molten salt carbonization process,capture and electrochemical conversion of CO_(2)to value-added carbon,electrochemical exfoliation of graphite to graphene-based materials,and electrochemical etching of carbides to new-type carbide-derived carbon *** reaction mechanisms and recent advances for these strategies are reviewed and discussed *** morphological and structural properties and capacitive performances of the obtained carbon materials are summarized to reveal their appealing points for supercapacitor ***,the opportunities and challenges of the molten salt synthesis strategy for the preparation of carbon materials are also discussed in this review to provide inspiration to the future researches.

关键词： Molten salt synthesis Porous carbon CO_(2)conversion Graphene Carbide-derived carbon

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Comparision between the Solid state Reaction of Ultrathin Ni and Ni/Ti with Si Nanowire on Soi Substrate

SSRN

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SSRN 2023年

作者： Gu, Sijie Shu, Gangqiang Hu, Chunfeng Qu, Xinping State Key Laboratory of ASIC and System School of Microelectronics Fudan University 220 Handan Road Shanghai200433 China

The morphology and phase transformation of nickel silicide nanowires with and without a titanium interlayer have been studied. 1 nm Ti film is sputtered as a metallic interlayer onto Si nanowires, then 10 nm Ni film is sputtered to form nickel silicide nanowires by rapid thermal annealing at 500℃ in N2 ambient. Nickel silicide nanowires without Ti interlayers tend to form Ni-rich phases, while the presence of a Ti layer reduces the nickel content in nickel silicide nanowires. Ni is excess in the whole nanowires with narrow line width, leading to the formation of silicide phases with a lower Ni ratio. The titanium interlayer acts as a diffusion barrier for Ni atoms and retards the Ni silicidation rate, causing a smoother interface between the nickel silicide nanowire and the silicon substrate. © 2023, The Authors. All rights reserved.

关键词： Nanowires

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Periodic Analysis of Adaptive LMS Filter in TIADC

Periodic Analysis of Adaptive LMS Filter in TIADC

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International Conference on asic

作者： Jiankun Li Zepeng Lin Fan Ye College of Microelectronics Fudan University Shanghai China State Key Laboratory of ASIC and System Fudan University Shanghai China

A periodic analysis of LMS adaptive filter in TI-ADC is presented. TI-ADC is a efficient technique to reach high sampling frequency but mismatches among different sub-ADCs influence its performance. LMS adaptive filter is a finite impulse response (FIR) filter which adapt itself to different inputs once implemented. To analyse SFDR performance of LMS filter in time domain, converged weigh vector and its analysis frequency domain are done theoretically and emulationally. Simulation shows that our theoretical analysis is consistent with the practical results that the useful range of SFDR performance is only negatively related to filter length if sampling frequency is constant. Further, it is concluded that there is a trade-off between maximum of SFDR in LMS filter and its useful range in terms of frequency.

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Monolithic Logic Units based on DCFL Structure on p-GaN platform for GaN ICs

Monolithic Logic Units based on DCFL Structure on p-GaN plat...

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International Conference on asic

作者： Maolin Pan Luyu Wang Qiang Wang Penghao Zhang Yuhang Wang Min Xu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Fudan University Shanghai China

GaN-based digital integrated circuits (ICs) are constructed on the commercially available GaN-on-Si p-GaN platform. The functions of inverter, NAND, AND, NOR, and OR logic circuits are successfully realized based on direct-coupled field-effect transistor logic (DCFL) structure. Under a drive voltage of 5V and a load ratio of 20, the low output (VOL) can reach as low as 0.1V. Additionally, a functional-oriented driver is constructed. All the transient tests at frequencies up to 100 kHz exhibit excellent performance characteristics.

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Integrated Device for Controllable Droplet Generation and Detection on Open Array Chip 16th

Integrated Device for Controllable Droplet Generation and De...

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16th International Conference on Intelligent Robotics and Applications, ICIRA 2023

作者： Zhou, Zijian Wang, Jie Li, Yuxin Zhou, Jia Du, Lin School of Mechanical Engineering University of Shanghai for Science and Technology Shanghai200433 China School of Optical-Electrical and Computer Engineering University of Shanghai for Science and Technology Shanghai200433 China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China

ISBN: (纸本)9789819965007

The open array chip is an incredibly valuable tool for analyzing single molecule levels. Its efficiency, speed, compatibility, and precision make it an essential part of this process. However, efficient sample addition has become a significant challenge in the development of open array chips due to the coupling of the solid-liquid interface and the need for high-precision control. To address this challenge, we have developed an integrated adding sample device using technology of generates and detects controllable droplets array based on an open array chip with a biomimetic structure. This device combines a microfluidic chip, image detection, and smear speed regulation. We have studied the factors that affect the efficiency of sample loading, such as the number, speed and fluctuation of smears, and microwell size. The experiments have shown that the open array chip with the microwell’s diameter of 350 µm can generate arrays of ~470/cm2 ~8 nL droplets, significantly reducing controlled speed fluctuation errors by7.24% and volume fluctuation errors by 24% compared to traditional manual ways. The device has also displayed excellent performance on chips with microwell diameters of 120, 350, 700, and 1300 µm, respectively, with a notable first-time success rate of up to 91% on chips with microwell diameters of 120 µm. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023.

关键词： Microfluidic chips

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A Monolithic GaN LDO Based on 12 V/0.5 μm GaN-on-Si Power Technology Achieving 20 ns Settling Time and 22 MHz UGF 16

A Monolithic GaN LDO Based on 12 V/0.5 μm GaN-on-Si Power T...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Wang, Peng Jiang, Yi-Zhou Liu, Dong-Sheng Zhang, You Li, Wen-Hong Huang, Wei Xiao, Zhi-Qiang Qiu, Yi-Wu Zhou, Xin-Jie Yang, Hong-Qiang Zhang, Wei Fudan University State Key Laboratory of Asic and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Shanghai200433 China Wuxi Microelectronics Scientific and Research Center Wuxi214035 China University of Electronic Science and Technology of China The State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu610054 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, a fast transient response capacitor-less gallium nitride (GaN)-based LDO on the GaN smart power technology platform for GaN integrated power regulation application is first proposed. A proposed GaN error amplifier (EA) with bootstrapping technology can effectively boost the gain to 45 dB. By employing the EA and a regulator enhancement-mode HEMT, the LDO is able to achieve a 22 MHz unit gain frequency with a load capacitor and current ranging from 0 pF to10 pF and 250 μA to 100mA, respectively. And the short settling time (20 ns) for 50-100 mA load change in 10 ns edge-time without load capacitor manifests superior high-frequency performance compared to silicon-based LDO. The circuit further promotes the development of an all-GaN solution compact power management system with improved reliability and performance. © 2022 IEEE.

关键词： Gallium nitride

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Millimeter-Wave AlGaN/GaN HEMTs/Si Operated on 12V for 5G RF Handset Applications 16

Millimeter-Wave AlGaN/GaN HEMTs/Si Operated on 12V for 5G RF...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Dong-Sheng Wang, Peng Jiang, Yi-Zhou Huang, Wei Xiao, Zhi-Qiang Yang, Hong-Qiang Zhang, Wei. Fudan University State Key Laboratory of Asic and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Shanghai200433 China Wuxi Microelectronics Scientific and Research Center Wuxi214035 China University of Electronic Science and Technology of China The State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu610054 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, a RF AlGaN/GaN high electron mobility transistor (HEMT) based on low voltage application of 5G RF handset, firstly fabricated on high-resistive silicon substrate is introduced, which uses Ni/Au as T-shaped gate structure and double-layer silicide as surface medium. The maximum output current density of the device is 1.07 A/mm at Vds = 12 V and Vgs = 2 V. fT = 27.8 GHz and BV (the breakdown voltage) = 35 V/μm are obtained for the 180-nm gate-length device with 1-μm source-to-gate spacing. © 2022 IEEE.

关键词： Silicides

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GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization

GRAEBO: FPGA General Routing Architecture Exploration via Ba...

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International Conference on Field Programmable Logic and Applications

作者： Su Zheng Jiadong Qian Hao Zhou Lingli Wang State Key Laboratory of ASIC & System School of Microelectronics Fudan University Shanghai China

Modern FPGAs utilize complex routing architectures to optimize the area, critical path delay, and power consumption. General Routing Block (GRB) models the routing resources of modern FPGAs, enabling the design of better routing architectures than previous academic FPGAs based on the CB-SB model. However, the design space of the GRB model is too large to be explored manually. In this paper, we propose GRAEBO, a design space exploration (DSE) algorithm for FPGA routing architectures based on Bayesian optimization, which can optimize and accelerate the DSE by balancing exploration and exploitation. Moreover, we design pruning rules to further improve the DSE efficiency, which can serve as a multi-fidelity acceleration method. GRAEBO obtains better area, delay, and area-delay product than a 142-channel baseline CB-SB architecture, with improvements of 8%, 19%, and 26%, respectively. Compared to the GRB architecture found by the simulated annealing algorithm, GRAEBO achieves 9% smaller area, 5% shorter delay, and 13% better area-delay product on the VTR benchmarks.

关键词： Power demand Simulated annealing Benchmark testing Routing Space exploration Delays Bayes methods

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Millimeter-Wave AlGaN/GaN HEMTs on Si Operated at 12V and its modeling for 5G Handset Applications

Millimeter-Wave AlGaN/GaN HEMTs on Si Operated at 12V and it...

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2023 Cross Strait Radio Science and Wireless Technology Conference, CSRSWTC 2023

作者： Wei, Zhen-Tao Liu, Dong-Sheng Huang, Wei Zhang, David Wei Li, Liang Ma, Hong-Ping Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics State Key Laboratory of ASIC and System Fudan University Shanghai200433 China School of Electronic Information Engineering Suzhou Vocational University Suzhou215104 China Fudan Univ Acad Engn & Technol Shanghai200433 China

ISBN: (纸本)9798350358971

关键词： 5G RF handset AlGaN/GaN HEMT high-resistive silicon substrate

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