检索结果-内蒙古大学图书馆

arXiv 2022年

作者： Song, Shuren Zhou, Jia Riaudy, Antoine State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

Surface acoustic waves (SAW) can concentrate micro-particles in droplets within seconds. Yet, the mechanism is not clear and existing explanations fail by several orders of magnitude. In this paper, we analyze the effect of fluid viscosity and particle size on SAW-driven collective particle dynamics in droplets. In most of our experiments, the particles do not aggregate but instead remain away from the droplet center, thereby forming "black holes". We show that the black holes are due to steric hindrance wherein the poloidal streamlines that should drive particles to the center of the droplet come too close to the solid, so that the particles carried along these streamlines touch the solid wall on the edge of the black hole before reaching the center of the droplet. The size of these black holes is correlated with the size of the aggregates formed in less viscous droplets. This suggests a common formation mechanism for black holes and white dwarfs (aggregates). In the former, the particles touching the solid would be washed away by the fluid, whereas in the latter the particles would remain in contact with the solid and roll to the center of the droplet where an aggregate is formed. We also discuss the stability conditions of the aggregate at the bottom of the droplet. The concept of hydrodynamic shielding is then used to concentrate 1 μm particles using 10 μm beads as shields. © 2022, CC BY.

关键词： Aggregates

来源：评论

学校读者我要写书评

暂无评论

Pocket assisted stepped tunneling to improve the band-to-band tunneling effect of nanotube TFETs

引用

microelectronics Journal 2025年 162卷

作者： Chen, Rui Han, Ruizhe Liu, Tao Shi, Xinlong Wang, Liming Zhang, Peijian Xu, Min Hu, Huiyong The Laboratory of Analog Integrated Circuits Hangzhou Institute of Technology Xidian University Hangzhou311231 China The State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China National Laboratory of Analog Integrated Circuits Chongqing400060 China

This paper proposes a stepped tunneling nanotube tunnel field-effect transistor (ST-NT-TFET). By introducing a source-side doped pocket with the same polarity within the TFET channel and employing asymmetric gate bias modulation, the device transforms point tunneling into a stepped tunneling pathway, thereby enhancing the band-to-band tunneling effect. Using Si0.5Ge0.5 as the source, the electrical characteristics and high-frequency performance of the ST-NT-TFET were investigated under different pocket parameters. Simulation results demonstrate that compared to conventional NT-TFETs with identical channel dimensions, the ST-NT-TFET achieves a 50% (p-TFET) and 109% (n-TFET) increase in on-state current, 92% (p) and 48% (n) enhancements in cut-off frequency, and 78% (p) and 66% boosts in gain-bandwidth product. The intrinsic delay is reduced by 55% (p) and 83% (n), while the effective drive current increases by 40% (p) and 135% (n). Circuit simulations further reveal that inverters constructed with ST-NT-TFETs exhibit a 27% increase in noise margin, 53% (fall time) and 31% (rise time) reductions in switching times, and an 11-stage ring oscillator frequency increased by 3.8 times (280% improvement). © 2025

关键词： Quartz

来源：评论

学校读者我要写书评

暂无评论

A 32-38GHz Full-360° Low-Phase-Error 6-bit Passive Phase Shifter in 0.15μm GaAs

A 32-38GHz Full-360° Low-Phase-Error 6-bit Passive Phase Sh...

引用

Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Luyao Wang Tianxiang Wu Wenyang Liu Yong Chen Junyan Ren Shunli Ma State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

A phase shifter is widely used in the phased array radar system and multi-beam antennas, which enables phased arrays for beam scanning by changing the phase of the corresponding radiating element. Based on GaAs $\boldsymbol{0.15}\mu \mathbf{m}$ process, this work researches and designs a 32-38GHz 6-bit phase shifter, in which the overall size of the chip is 1.87 mm $\times 1.5$ mm. The proposed phase shifter is designed using high and low pass filter types for $\boldsymbol{180}^{\circ}$ and $\boldsymbol{90}^{\circ}$ units. In order to alleviate the problem of too-large inductance and too-small capacitance, this work uses Low-pass and bypass filter types for $\boldsymbol{45}^{\circ}, \boldsymbol{22.5}^{\circ}\boldsymbol{11.25}^{\circ}$ , and $\boldsymbol{5.625}^\circ$ units. The RMS phase shift error of this 6-bit phase shifter is less than $\boldsymbol{4}^{\circ}$ .

关键词：

来源：评论

学校读者我要写书评

暂无评论

A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm

A High-Speed NTT-Based Polynomial Multiplication Accelerator...

引用

IEEE Asia-Pacific Conference on Circuits and systems

作者： Honglin Kuang Yifan Zhao Jun Han State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

Saber is a module-learning with rounding-based post-quantum cryptography (PQC) scheme for key encapsulation mechanism (KEM). It is characterized by the use of power-of-two moduli, which makes all modulus reductions free in hardware. However, such a decision prevents the direct implementation of the asymptotically fastest number theoretic transform (NTT) for the time-consuming polynomial multiplication in Saber. To efficiently multiply polynomials, researches have been done using a schoolbook or Toom-Cook or Karatsuba algorithm. Though these approaches result in decent operating speed at moderate area cost, they are disadvantageous when considering expanding the system to support multiple PQC protocols. To enable NTT for Saber, we choose an appropriate prime and use the sign-magnitude format for computation. A concise and efficient vectorized NTT algorithm has been proposed, based on which we design a configurable vector NTT unit to perform NTT and other arithmetic operations. The accelerator is dedicatedly pipelined to achieve high speed and is driven by custom vector instruction extension of RISC-V. We implement the proposed architecture with vector lanes of 32 and 16 on Xilinx UltraScale+ ZCU111. Results show that our design can achieve up to $5\mathrm{x}$ and $3\mathrm{x}$ improvement in computation time and area-time-product (ATP) respectively for degree-256 polynomials multiplication, compared to the state-of-the-art Saber polynomial multiplier counterparts.

关键词： Encapsulation Protocols Costs Circuits and systems Asia Transforms Computer architecture

来源：评论

学校读者我要写书评

暂无评论

A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC

A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successiv...

引用

IEEE Asia-Pacific Conference on Circuits and systems

作者： Yutong Zhao Fan Ye Junyan Ren State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

This paper presents a 500-MS/s 9-bit time-domain analog-to-digital converter (ADC) using a nonbinary successive approximation time-to-digital converter (SA TDC) for energy efficiency and high linearity. By adding redundancy in the first six decision steps, the delay fluctuations of the delay cells and offset of the time-domain comparators in the SA TDC can be tolerated and nonlinearity can thus be reduced. In addition, a voltage-to-time converter (VTC) with a voltage-boost scheme is utilized to expand the linear dynamic range. Simulated in 28nm CMOS, the time-domain ADC consumes 4.27 mW under supply voltages of 0.9 V and 2.5 V. It is shown that SNDR and SFDR are 54.69 dB and 55.16 dB at Nyquist input frequency operating at a 500-MS/s sampling rate, respectively, resulting in a Walden figure of merit (FOMw) of 19.29 fJ/conversion step.

关键词： Rails Time-frequency analysis Fluctuations Power demand Redundancy Linearity Dynamic range

来源：评论

学校读者我要写书评

暂无评论

Energy-aware Retinaface: A Power Efficient Edge-Computing SOC for Face Detector in 40nm 14

Energy-aware Retinaface: A Power Efficient Edge-Computing SO...

引用

14th IEEE International Conference on asic, asicON 2021

作者： Sun, Miao Cao, Yingjie Chiang, Patrick Yin Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai China TiMESiNTELLi Inc. Shanghai China

ISBN: (纸本)9781665411493

In this work, an energy-awaring face detector is implemented in 40nm technology SoC. Based on the art-of-state face detector, a highest accuracy retinaface detector (91.4% average precision) on the WIDER FACE dataset is quantized in the int8 domain. For this neural network, an 8-bit CNN accelerator in a hybrid SOC architecture is designed to achieve an end-to-end face detector. The entire detector runs at 15fps with 66.67mw power per frame. Furthermore, redundant layers in this CNN are analyzed based on this performance. For different sizes of face, some calculations can be reduced with no loss brought to results. To address this improvement, this network is divided into three branches according to different sizes of faces in a single input image. Besides, a simple two-layer classifier is trained to determine the calculation graph in the current run and implemented on SOC. Finally, the face detector increases to 36fps, and energy power decreases to 27.78mw power per frame. This is the highest accuracy(85.8%) face detector hardware implementation on the WILDER FACE dataset. © 2021 IEEE.

关键词： Face recognition

来源：评论

学校读者我要写书评

暂无评论

Automated Design of Analog Circuits Based on Parallel Trust Region Bayesian Optimization

Automated Design of Analog Circuits Based on Parallel Trust ...

引用

Electronics Design Automation (ISEDA), International Symposium of

作者： Peng Dong Ruiyu Lyu Chunxi Wang Jiale Chen Linfeng Jiang Cunqing Lan Zhaori Bi Changhao Yan Microelectronics Department State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China Huawei Technologies Co Ltd National ASIC System Engineering Center Southeast University Nanjing China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

Traditional optimization algorithms suffer performance decline in high-dimensional optimization problems, such as analog circuit design optimization. Adapting existing algorithms to parallel computing environments is a critical challenge. Therefore we propose a parallel Trust Region Bayesian Optimization(TuRBO) algorithm. This algorithm operates in parallel on different trust regions, utilizing a Multi-Armed Bandit algorithm for intelligent sampling to accelerate parameter optimization. Circuit experimental results demonstrate the advantages of this algorithm. Compared to Differential Evolution, Particle Swarm Optimization, Naive Bayesian, High-Dimensional Batch Bayesian Processing, and TuRBO algorithms, the circuit performance achieves improvements ranging from 3.7% to 98.2%. Compared to TuRBO, it achieves acceleration ratios in terms of iteration numbers ranging from 1.19x to 1.31x, and in terms of algorithm runtime ranging from 1.21x to 2.25x.

关键词： Runtime Design automation Heuristic algorithms Parallel processing Distance measurement Bayes methods Resource management

来源：评论

学校读者我要写书评

暂无评论

Analog and Logic Circuits Fabricated on a Wafer-Scale Two-Dimensional Semiconductor

Analog and Logic Circuits Fabricated on a Wafer-Scale Two-Di...

引用

2022 International Symposium on VLSI Technology, systems and Applications, VLSI-TSA 2022

作者： Wang, Xinyu Chen, Xinyu Ma, Jingyi Chen, Honglei Gou, Saifei Guo, Xiaojiao Tong, Ling Xia, Yin Xu, Zihan Zhou, Peng Wu, Chenjian Bao, Wenzhong Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai200433 China Shenzhen Six Carbon Technology Shenzhen518055 China Soochow University School of Electronic Information Suzhou215006 China

ISBN: (纸本)9781665409230

MoS2 is a typical two-dimensional (2D) semiconductor with extraordinary electrical properties, and has been intensively investigated as a channel material for field-effect transistors (FETs) and logic circuits in recent years. In this work, the top gated (TG) MoS2 FETs are fabricated with wafer-scale uniformity, and several pivotal devices and circuits based on MoS2 films are demonstrated, including current mirrors, inverter, and the AND/OR logic circuits. All devices exhibit reliable electrical characteristics, which lays the foundation for the future fabrication of large-scale MoS2 circuits. © 2022 IEEE.

关键词： Molybdenum compounds

来源：评论

学校读者我要写书评

暂无评论

The Electrical-thermal Coupling Modeling about Large Periphery RF GaN HEMT on Si employing by Through Wafer Via Structure 16

The Electrical-thermal Coupling Modeling about Large Periphe...

引用

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Wei, Zhen-Tao Jiang, Yi-Zhou Wang, Ying-Sheng Huang, Wei Xiao, Zhi-Qiang Zhang, Wei Fudan University State Key Laboratory of Asic and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Shanghai200433 China Nanjing Electronic Device Institute Nanjing210016 China Wuxi Microelectronics Scientific and Research Center Wuxi214035 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Non-uniform thermal distribution affects about large periphery GaN HEMT based on through-via structure is analyzed in the paper. According to the self-heating effect and heat dissipation issues of Si-based GaN HEMT RF power devices, a high density through-via technology employing by conducting thermal near junction of multi-gate finger device downward to the heat sink is further put forward. Its corresponding placement provide a novel path for spreading heat directly from the heat source region of each of cell to the low temperature heat sink. From the thermal simulation with a total gate width of 8.1 mm, it is shown that compared with traditional structure devices, the maximum junction temperature of a uniform gate device with through-via structure is reduced by 34 °C, and the thermal resistance is reduced by 1.05 °C /W. Therefore, the through via technology as key process can play an important role in developing the large periphery RF GaN HEMT on high resistance Si substrate. © 2022 IEEE.

关键词： Heat sinks

来源：评论

学校读者我要写书评

暂无评论

Large circuit models: opportunities and challenges

引用

Science China(Information Sciences) 2024年第10期67卷 25-66页

作者： Lei CHEN Yiqi CHEN Zhufei CHU Wenji FANG Tsung-Yi HO Ru HUANG Yu HUANG Sadaf KHAN Min LI Xingquan LI Yu LI Yun LIANG Jinwei LIU Yi LIU Yibo LIN Guojie LUO Hongyang PAN Zhengyuan SHI Guangyu SUN Dimitrios TSARAS Runsheng WANG Ziyi WANG Xinming WEI Zhiyao XIE Qiang XU Chenhao XUE Junchi YAN Jun YANG Bei YU Mingxuan YUAN Evangeline F.Y.YOUNG Xuan ZENG Haoyi ZHANG Zuodong ZHANG Yuxiang ZHAO Hui-Ling ZHEN Ziyang ZHENG Binwu ZHU Keren ZHU Sunan ZOU Huawei Noah’s Ark Lab School of Integrated Circuits Peking University Faculty of Electrical Engineering and Computer Science Ningbo University Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Department of Computer Science and Engineering The Chinese University of Hong Kong School of Integrated Circuits Southeast University Huawei HiSilicon Peng Cheng Laboratory School of Computer Science Peking University School of Microelectronics State Key Laboratory of Integrated Chips and System Fudan University School of Artificial Intelligence Shanghai Jiao Tong University

Within the electronic design automation(EDA) domain, artificial intelligence(AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an “AI4EDA” approach falls short of achieving a holistic design synthesis and understanding,overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This study argues for a paradigm shift from AI4EDA towards AI-rooted EDA from the ground up, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, register-transfer level(RTL) designs, circuit netlists,and physical layouts. We champion the creation of large circuit models(LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-rooted philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound “shift-left” in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design-tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area(PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems' capabilities.

关键词： AI-rooted EDA large circuit models (LCMs) multimodal circuit representation learning circuit optimization

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：